From 8c4445d26633f43fcd04add3d6cdc3bc41d14841 Mon Sep 17 00:00:00 2001 From: Peter Barada Date: Tue, 13 Nov 2012 07:40:28 +0000 Subject: Pass sdrc timing values through board_sdrc_timings structure Instead of passing individual registers by value to board_get_mem_timings, pass a board_mem_timings structure pointer for the board files to fill in. Pass same structure pointer to write_sdrc_timings. This saves about 90 bytes of space in SPL. Signed-off-by: Peter Barada --- board/corscience/tricorder/tricorder.c | 13 ++++----- board/isee/igep0020/igep0020.c | 29 +++++++++---------- board/isee/igep0030/igep0030.c | 29 +++++++++---------- board/overo/overo.c | 37 ++++++++++++------------ board/ti/beagle/beagle.c | 53 +++++++++++++++++----------------- board/ti/evm/evm.c | 19 ++++++------ board/timll/devkit8000/devkit8000.c | 13 ++++----- 7 files changed, 93 insertions(+), 100 deletions(-) (limited to 'board') diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index aaff2e868ba..56fe495277e 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -91,15 +91,14 @@ int board_mmc_init(bd_t *bis) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->mr = MICRON_V_MR_165; } diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index a8257a3005f..a0f2aa3e4e2 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -72,27 +72,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 107cb7f8e05..a41e752b820 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -59,27 +59,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/overo/overo.c b/board/overo/overo.c index c6d50a07aca..fdf46a2aae9 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -147,34 +147,33 @@ int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = MICRON_V_MCFG_165(256 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = HYNIX_V_MCFG_165(256 << 20); - *ctrla = HYNIX_V_ACTIMA_165; - *ctrlb = HYNIX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_165(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_165; + timings->ctrlb = HYNIX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; default: - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6175e1d1ac0..4adf9827c5f 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -139,8 +139,7 @@ static int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -151,29 +150,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, */ identify_nand_chip(&pop_mfr, &pop_id); - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) { /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { /* Beagleboard Rev C5, 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; } case REVISION_XM_A: @@ -181,24 +180,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, case REVISION_XM_C: if (pop_mfr == 0) { /* 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } else { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } break; default: /* Assume 128MB and Micron/165MHz timings to be safe */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 61fc7b55310..8a3aa0c5bfd 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -128,8 +128,7 @@ int board_init(void) * provides the timing values back to the function that configures * the memory. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -142,17 +141,17 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { /* 256MB DDR */ - *mcfg = HYNIX_V_MCFG_200(256 << 20); - *ctrla = HYNIX_V_ACTIMA_200; - *ctrlb = HYNIX_V_ACTIMB_200; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; } else { /* 128MB DDR */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; } - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - *mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = MICRON_V_MR_165; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 35f5e15fc24..85685ee7c05 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -188,16 +188,15 @@ int spl_start_uboot(void) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; } -- cgit v1.2.3