From 81b73dec16fd1227369a191e725e10044a9d56b8 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 15:21:46 +0200 Subject: ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese --- board/amcc/sequoia/init.S | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 45bcd4bef75..5fe3af9a092 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -126,6 +126,9 @@ tlbtab: /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -- cgit v1.2.3