From 63e75fd7a3808df091eb50786519703c5df76b8e Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 26 Sep 2014 16:25:32 +0800 Subject: qe: add qe support to ls1021aqds add qe support to ls1021aqds Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- board/freescale/ls1021aqds/ls1021aqds.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board/freescale') diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 5fafc85672..bcfa9b9556 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -17,6 +17,9 @@ #include "../common/qixis.h" #include "ls1021aqds_qixis.h" +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -237,6 +240,11 @@ int board_init(void) fsl_serdes_init(); config_serdes_mux(); #endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + return 0; } -- cgit v1.2.3 From eaa859e7d23172acb68b3096beb083ba2e42d6c3 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 26 Sep 2014 16:25:33 +0800 Subject: qe: add qe support for ls1021a-twr board Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- board/freescale/ls1021atwr/ls1021atwr.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board/freescale') diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 50d564055b..a90bb09152 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -17,6 +17,10 @@ #include #include #include +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -278,6 +282,10 @@ int board_init(void) config_serdes_mux(); #endif +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + return 0; } -- cgit v1.2.3 From 644bc7ec5cee3a93ecb3adc364be6374d3f60a27 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 17 Oct 2014 15:26:32 +0800 Subject: arm: ls102xa: Add snoop disable for slave port 0, 1 and 2 Disable the snoop for slave interface 0, 1 and 2 to avoid the interleaving on the CCI400 BUS. Signed-off-by: Jason Jin Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- board/freescale/ls1021aqds/ls1021aqds.c | 7 +++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 2 files changed, 17 insertions(+) (limited to 'board/freescale') diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index bcfa9b9556..5154a85b2d 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -233,6 +233,13 @@ int board_init(void) /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index a90bb09152..3e8981b39f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -277,6 +277,16 @@ int board_early_init_f(void) int board_init(void) { + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); config_serdes_mux(); -- cgit v1.2.3 From c207ff612903389f8b32e377fe32be43e6efd8f7 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Fri, 17 Oct 2014 15:26:33 +0800 Subject: arm: ls102xa: Remove bit reversing for SCFG registers SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode. Address: 157_0000h base + 200h offset = 157_0200h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W/R SCFGREV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31 SCFGREV SCFG Bit Reverse Control Filed 32'h 0000_0000 - No bit reverse is applied 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31 This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi write 0x570200, 0xffffffff .end So other SCFG register could be written in big-endian mode in u-boot or kernel directly. Signed-off-by: Alison Wang Reviewed-by: York Sun --- board/freescale/ls1021aqds/ls1021aqds.c | 2 -- board/freescale/ls1021atwr/ls1021atwr.c | 5 ----- 2 files changed, 7 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 5154a85b2d..913dda92c5 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -140,9 +140,7 @@ int board_early_init_f(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); #endif #ifdef CONFIG_FSL_IFC diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 3e8981b39f..3f2dc1acad 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -255,11 +255,8 @@ int board_early_init_f(void) struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); - udelay(10); - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); #endif #ifdef CONFIG_FSL_IFC @@ -267,9 +264,7 @@ int board_early_init_f(void) #endif #ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); #endif return 0; -- cgit v1.2.3 From 5175a2885fbb47e4836dcb8ad0ad2214e9b0b3b5 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Fri, 17 Oct 2014 15:26:35 +0800 Subject: arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board. As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC. As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot. Signed-off-by: Alison Wang Reviewed-by: York Sun --- board/freescale/common/sys_eeprom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 6144c533ef..3426b8ada3 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -90,7 +90,7 @@ static void show_eeprom(void) /* EEPROM tag ID, either CCID or NXID */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); + e.version); #else printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif @@ -485,7 +485,7 @@ int mac_read_from_eeprom(void) #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); + e.version); #else printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif -- cgit v1.2.3 From 0ab172353e14dbdb7278755de6feae3fc4b54c2f Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Fri, 17 Oct 2014 15:26:36 +0800 Subject: arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1 as other functionality except RGMII. The workaround is to select ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR. Signed-off-by: Alison Wang Reviewed-by: York Sun --- board/freescale/ls1021aqds/ls1021aqds.c | 1 + 1 file changed, 1 insertion(+) (limited to 'board/freescale') diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 913dda92c5..d64b24c417 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -141,6 +141,7 @@ int board_early_init_f(void) #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif #ifdef CONFIG_FSL_IFC -- cgit v1.2.3