From e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 4 May 2016 10:20:22 +0800 Subject: board/freescale: Update ddr clk_adjust This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t1040qds/ddr.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'board/freescale/t1040qds') diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index a6e1673525..1e087460cb 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, #else #error DDR type not defined #endif -- cgit v1.2.3