From 6525d51fa5790727c04c4883341bc8f58f8e3bb3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 8 Jul 2010 22:37:44 -0500 Subject: powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/pci.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) (limited to 'board/freescale/p1_p2_rdb/pci.c') diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index aa2f64ca91..97d4f834b0 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -100,16 +100,5 @@ void pci_init_board(void) void ft_pci_board_setup(void *blob) { -/* According to h/w manual, PCIE2 is at lower address(0x9000) - * than PCIE1(0xa000). - * Hence PCIE2 is made to occupy the pci1 position in dts to - * keep the addresses sorted there. - * Generally the case with all FSL SOCs. - */ -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; } -- cgit v1.2.3