From 6a133d6a00b1fc7b9257cd5925d8cb67f75ecda2 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 7 Oct 2008 13:13:08 +0200 Subject: ppc4xx: Fix DU440 GPIO configuration Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/du440/du440.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'board/esd') diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 8765cc1f3e1..5cff9f5f48f 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -52,15 +52,15 @@ int board_early_init_f(void) * Setup the GPIO pins */ out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP); - out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP); + out_be32((void*)GPIO0_TCR, 0x0000001f | CFG_GPIO0_EP_EEP); out_be32((void*)GPIO0_OSRL, 0x50055400); - out_be32((void*)GPIO0_OSRH, 0x550050aa); + out_be32((void*)GPIO0_OSRH, 0x55005000); out_be32((void*)GPIO0_TSRL, 0x50055400); out_be32((void*)GPIO0_TSRH, 0x55005000); out_be32((void*)GPIO0_ISR1L, 0x50000000); out_be32((void*)GPIO0_ISR1H, 0x00000000); out_be32((void*)GPIO0_ISR2L, 0x00000000); - out_be32((void*)GPIO0_ISR2H, 0x00000100); + out_be32((void*)GPIO0_ISR2H, 0x00000000); out_be32((void*)GPIO0_ISR3L, 0x00000000); out_be32((void*)GPIO0_ISR3H, 0x00000000); @@ -73,9 +73,9 @@ int board_early_init_f(void) CFG_GPIO1_LEDPOST | CFG_GPIO1_LEDDU); out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU); - out_be32((void*)GPIO1_OSRL, 0x5c280000); + out_be32((void*)GPIO1_OSRL, 0x0c280000); out_be32((void*)GPIO1_OSRH, 0x00000000); - out_be32((void*)GPIO1_TSRL, 0x0c000000); + out_be32((void*)GPIO1_TSRL, 0xcc000000); out_be32((void*)GPIO1_TSRH, 0x00000000); out_be32((void*)GPIO1_ISR1L, 0x00005550); out_be32((void*)GPIO1_ISR1H, 0x00000000); -- cgit v1.2.3 From df8c1ce11114c2260dedb5547281945f7db8fa5c Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 7 Oct 2008 13:13:09 +0200 Subject: ppc4xx: Add strapping mode for 667MHz CPU frequency on DU440 board Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/du440/du440.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board/esd') diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 5cff9f5f48f..7df2adb238e 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -733,6 +733,12 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* sdsdp[1]=0x095fa030; */ sdsdp[2] = 0x40082350; sdsdp[3] = 0x0d050000; + } else if (!strcmp(argv[1], "667-166")) { + printf("Bootstrapping for 667-166MHz\n"); + sdsdp[0] = 0x8778a252; + sdsdp[1] = 0x09d7a030; + sdsdp[2] = 0x40082350; + sdsdp[3] = 0x0d050000; } } else { printf("Bootstrapping for 533MHz (default)\n"); -- cgit v1.2.3 From 542b385a620a1783454a00424930e51895f45073 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 7 Oct 2008 13:13:10 +0200 Subject: ppc4xx: Fix USB 2.0 phy reset sequence This patch fixes USB 2.0 communication issues on some DU440 boards. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/du440/du440.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) (limited to 'board/esd') diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 7df2adb238e..6dca35d6267 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -169,6 +169,7 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; + unsigned long sdr0_srst0, sdr0_srst1; int i, j; /* adjust flash start and offset */ @@ -223,10 +224,38 @@ int misc_init_r(void) mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); - /* clear resets */ - udelay (1000); + /* + * Take USB out of reset: + * -Initial status = all cores are in reset + * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores + * -wait 1 ms + * -deassert reset to PHY + * -wait 1 ms + * -deassert reset to HOST + * -wait 4 ms + * -deassert all other resets + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ + SDR0_SRST1_P4OPB0 | \ + SDR0_SRST1_OPBA2 | \ + SDR0_SRST1_PLB42OPB1 | \ + SDR0_SRST1_OPB2PLB40); + mtsdr(SDR0_SRST1, sdr0_srst1); + udelay(1000); + + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst1); + udelay(1000); + + mfsdr(SDR0_SRST0, sdr0_srst0); + sdr0_srst0 &= ~SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst0); + udelay(4000); + + /* finally all the other resets */ mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy)\n"); -- cgit v1.2.3 From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/esd/adciop/flash.c | 2 +- board/esd/apc405/apc405.c | 58 +++++++-------- board/esd/ar405/flash.c | 4 +- board/esd/ash405/ash405.c | 8 +-- board/esd/ash405/flash.c | 4 +- board/esd/canbt/flash.c | 2 +- board/esd/cms700/cms700.c | 30 ++++---- board/esd/cms700/flash.c | 4 +- board/esd/common/auto_update.c | 6 +- board/esd/common/esd405ep_nand.c | 18 ++--- board/esd/common/flash.c | 136 +++++++++++++++++------------------ board/esd/common/fpga.c | 18 ++--- board/esd/common/lcd.c | 34 ++++----- board/esd/common/pci.c | 22 +++--- board/esd/common/xilinx_jtag/ports.h | 10 +-- board/esd/cpci2dp/cpci2dp.c | 28 ++++---- board/esd/cpci2dp/flash.c | 2 +- board/esd/cpci405/cpci405.c | 46 ++++++------ board/esd/cpci405/flash.c | 2 +- board/esd/cpci5200/cpci5200.c | 14 ++-- board/esd/cpci5200/strataflash.c | 22 +++--- board/esd/cpci750/cpci750.c | 134 +++++++++++++++++----------------- board/esd/cpci750/i2c.c | 8 +-- board/esd/cpci750/ide.c | 8 +-- board/esd/cpci750/local.h | 2 +- board/esd/cpci750/misc.S | 26 +++---- board/esd/cpci750/mpsc.c | 6 +- board/esd/cpci750/pci.c | 20 +++--- board/esd/cpci750/sdram_init.c | 8 +-- board/esd/cpciiser4/flash.c | 2 +- board/esd/dasa_sim/cmd_dasa_sim.c | 14 ++-- board/esd/dasa_sim/flash.c | 2 +- board/esd/dp405/flash.c | 4 +- board/esd/du405/flash.c | 2 +- board/esd/du440/config.mk | 2 +- board/esd/du440/du440.c | 124 ++++++++++++++++---------------- board/esd/du440/du440.h | 20 +++--- board/esd/du440/init.S | 26 +++---- board/esd/du440/u-boot.lds | 2 +- board/esd/hh405/flash.c | 4 +- board/esd/hh405/hh405.c | 86 +++++++++++----------- board/esd/hub405/flash.c | 4 +- board/esd/hub405/hub405.c | 14 ++-- board/esd/mecp5200/mecp5200.c | 16 ++--- board/esd/ocrtc/flash.c | 2 +- board/esd/pci405/flash.c | 2 +- board/esd/pci405/pci405.c | 16 ++--- board/esd/pf5200/flash.c | 24 +++---- board/esd/pf5200/pf5200.c | 18 ++--- board/esd/plu405/flash.c | 4 +- board/esd/plu405/plu405.c | 42 +++++------ board/esd/pmc405/pmc405.c | 36 +++++----- board/esd/pmc440/cmd_pmc440.c | 14 ++-- board/esd/pmc440/config.mk | 2 +- board/esd/pmc440/init.S | 26 +++---- board/esd/pmc440/pmc440.c | 56 +++++++-------- board/esd/pmc440/pmc440.h | 4 +- board/esd/pmc440/sdram.c | 2 +- board/esd/pmc440/u-boot.lds | 2 +- board/esd/tasreg/flash.c | 8 +-- board/esd/tasreg/tasreg.c | 16 ++--- board/esd/voh405/flash.c | 4 +- board/esd/voh405/voh405.c | 62 ++++++++-------- board/esd/vom405/flash.c | 4 +- board/esd/wuh405/flash.c | 4 +- board/esd/wuh405/wuh405.c | 8 +-- 66 files changed, 680 insertions(+), 680 deletions(-) (limited to 'board/esd') diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c index d9eccba1ea8..dd578c8939b 100644 --- a/board/esd/adciop/flash.c +++ b/board/esd/adciop/flash.c @@ -45,7 +45,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; iboard_type >= 6) { - result = lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13505_640_480_16bpp, sizeof(regs_13505_640_480_16bpp) / sizeof(regs_13505_640_480_16bpp[0]), @@ -332,16 +332,16 @@ int misc_init_r(void) /* retry with internal image */ logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13505_640_480_16bpp, sizeof(regs_13505_640_480_16bpp) / sizeof(regs_13505_640_480_16bpp[0]), logo_addr, logo_size); } } else { - result = lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp) / sizeof(regs_13806_640_480_16bpp[0]), @@ -350,8 +350,8 @@ int misc_init_r(void) /* retry with internal image */ logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp) / sizeof(regs_13806_640_480_16bpp[0]), @@ -389,12 +389,12 @@ int misc_init_r(void) * fix environment for field updated units */ if (getenv("altbootcmd") == NULL) { - setenv("usb_load", CFG_USB_LOAD_COMMAND); - setenv("usbargs", CFG_USB_ARGS); + setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND); + setenv("usbargs", CONFIG_SYS_USB_ARGS); setenv("bootcmd", CONFIG_BOOTCOMMAND); - setenv("usb_self", CFG_USB_SELF_COMMAND); - setenv("bootlimit", CFG_BOOTLIMIT); - setenv("altbootcmd", CFG_ALT_BOOTCOMMAND); + setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND); + setenv("bootlimit", CONFIG_SYS_BOOTLIMIT); + setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND); saveenv(); } @@ -426,17 +426,17 @@ int checkboard (void) #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { - u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); /* * Assert or deassert CompactFlash Reset Pin */ if (on) { out_be16(fpga_mode, - in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET); + in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET); } else { out_be16(fpga_mode, - in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET); + in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET); } } #endif /* CONFIG_IDE_RESET */ @@ -449,7 +449,7 @@ void reset_phy(void) lxt971_no_sleep(); } -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) int usb_board_init(void) { return 0; @@ -480,4 +480,4 @@ int usb_board_init_fail(void) usb_board_stop(); return 0; } -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c index 89af1190a8a..274ada9fe5c 100644 --- a/board/esd/ar405/flash.c +++ b/board/esd/ar405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i I2C address of EEPROM device to enable. * -1: deliver current state * 0: disable write @@ -143,23 +143,23 @@ int checkboard (void) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -173,21 +173,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -200,7 +200,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ /* ------------------------------------------------------------------------- */ diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c index 89af1190a8a..274ada9fe5c 100644 --- a/board/esd/cms700/flash.c +++ b/board/esd/cms700/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; ipriv; if (ctrl & NAND_CTRL_CHANGE) { if ( ctrl & NAND_CLE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE); if ( ctrl & NAND_ALE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE); else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE); if ( ctrl & NAND_NCE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE); else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); } if (cmd != NAND_CMD_NONE) @@ -58,7 +58,7 @@ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int */ static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) { - if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY) + if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY) return 1; return 0; } @@ -69,8 +69,8 @@ int board_nand_init(struct nand_chip *nand) /* * Set NAND-FLASH GPIO signals to defaults */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); /* * Initialize nand_chip structure diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c index bda361ead94..3ea053b8cc4 100644 --- a/board/esd/common/flash.c +++ b/board/esd/common/flash.c @@ -27,7 +27,7 @@ #endif #include -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -167,7 +167,7 @@ void flash_print_info (flash_info_t *info) printf (" Sector Start Addresses:"); for (i=0; isector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO /* * Check if whole sector is erased */ @@ -221,28 +221,28 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) { short i; short n; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong)addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - value = addr2[CFG_FLASH_READ0]; + value = addr2[CONFIG_SYS_FLASH_READ0]; switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; default: @@ -252,104 +252,104 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) return (0); /* no or unknown flash */ } - value = addr2[CFG_FLASH_READ1]; /* device ID */ + value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: info->flash_id += FLASH_AMDL322T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: info->flash_id += FLASH_AMDL322B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: info->flash_id += FLASH_AMDL323T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: info->flash_id += FLASH_AMDL323B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U: info->flash_id += FLASH_AM640U; info->sector_count = 128; info->size = 0x00800000; break; /* => 8 MB */ #if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM)) - case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A: info->flash_id += FLASH_SST800A; info->sector_count = 16; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602: info->flash_id += FLASH_SST160A; info->sector_count = 32; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202: info->flash_id += FLASH_SST320; info->sector_count = 64; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402: info->flash_id += FLASH_SST640; info->sector_count = 128; info->size = 0x00800000; @@ -424,19 +424,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) info->protect[i] = 0; else - info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; } /* * Prevent writes to uninitialized FLASH. */ if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ } return (info->size); @@ -448,8 +448,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; ulong start, now, last; int i; @@ -490,25 +490,25 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */ for (i=0; i<50; i++) udelay(1000); /* wait 1 ms */ } else { if (sect == s_first) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; } - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ } l_sect = sect; } @@ -529,9 +529,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) start = get_timer (0); last = start; - addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -544,8 +544,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) DONE: /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ printf (" done\n"); return 0; @@ -630,9 +630,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word (flash_info_t *info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; ulong start; int flag; int i; @@ -645,11 +645,11 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) + for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; dest2[i] = data2[i]; @@ -659,9 +659,9 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c index 9e2be7eaf04..5232dddc9e8 100644 --- a/board/esd/common/fpga.c +++ b/board/esd/common/fpga.c @@ -36,12 +36,12 @@ #define MAX_ONES 226 -#ifdef CFG_FPGA_PRG -# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output) */ -# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ +#ifdef CONFIG_SYS_FPGA_PRG +# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */ +# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */ +# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */ +# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */ +# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */ #else # define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ # define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ @@ -98,7 +98,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size) int count; unsigned char b; -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 int j; #else int bit; @@ -112,7 +112,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size) index += len + 3; } -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* search for preamble 0xFFFFFFFF */ while (1) { if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) @@ -186,7 +186,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size) DBG ("write configuration data into fpga\n"); /* write configuration-data into fpga... */ -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* * Load uncompressed image into fpga */ diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index c23dc81a266..1eea59ecb12 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -37,7 +37,7 @@ int lcd_depth; unsigned char *glob_lcd_reg; unsigned char *glob_lcd_mem; -#if defined(CFG_LCD_ENDIAN) +#if defined(CONFIG_SYS_LCD_ENDIAN) void lcd_setup(int lcd, int config) { if (lcd == 0) { @@ -47,21 +47,21 @@ void lcd_setup(int lcd, int config) /* set reset to low */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST); udelay(10); /* wait 10us */ if (config == 1) { /* big-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); } else { /* little-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); } udelay(10); /* wait 10us */ /* set reset to high */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST); } else { /* * Set endianess and reset lcd controller 1 (big) @@ -69,29 +69,29 @@ void lcd_setup(int lcd, int config) /* set reset to low */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST); udelay(10); /* wait 10us */ if (config == 1) { /* big-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); } else { /* little-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); } udelay(10); /* wait 10us */ /* set reset to high */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST); } /* - * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive + * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); } -#endif /* CFG_LCD_ENDIAN */ +#endif /* CONFIG_SYS_LCD_ENDIAN */ int lcd_bmp(uchar *logo_bmp) @@ -116,20 +116,20 @@ int lcd_bmp(uchar *logo_bmp) /* * Decompress bmp image */ - len = CFG_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { printf("Error: malloc for gunzip failed!\n"); return 1; } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, + if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) { free(dst); return 1; } - if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { printf("Image could be truncated" - " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); } /* diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c index f711205efe5..dcb764cd1f3 100644 --- a/board/esd/common/pci.c +++ b/board/esd/common/pci.c @@ -119,24 +119,24 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d /* * Configure PLX PCI9054 */ - pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); + pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status); status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); + pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status); /* Check the latency timer for values >= 0x60. */ - pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); + pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); if (timer < 0x60) { - pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); + pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); } /* Set I/O base register. */ - pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); - pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); + pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE); + pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); + pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); if (pci9054_iobase == 0xffffffff) { @@ -149,13 +149,13 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d static struct pci_config_table pci9054_config_table[] = { #ifndef CONFIG_PCI_PNP { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), - pci_cfgfunc_config_device, { CFG_ETH_IOBASE, - CFG_ETH_IOBASE, + PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN), + pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE, + CONFIG_SYS_ETH_IOBASE, PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, #ifdef CONFIG_DASA_SIM { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), + PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN), pci_dasa_sim_config_pci9054 }, #endif #endif diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h index 0e389907ff6..b702fdd9a78 100644 --- a/board/esd/common/xilinx_jtag/ports.h +++ b/board/esd/common/xilinx_jtag/ports.h @@ -38,12 +38,12 @@ #define TDI (short) 2 /* - * Use CFG_FPGA_xxx defines from board include file. + * Use CONFIG_SYS_FPGA_xxx defines from board include file. */ -#define JTAG_TMS CFG_FPGA_PRG /* output */ -#define JTAG_TCK CFG_FPGA_CLK /* output */ -#define JTAG_TDI CFG_FPGA_DATA /* output */ -#define JTAG_TDO CFG_FPGA_DONE /* input */ +#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */ +#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */ +#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */ +#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */ /* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */ void setPort(short p, short val); diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 8bc40d5a2f0..dcab9060b66 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -36,12 +36,12 @@ int board_early_init_f (void) * Setup GPIO pins */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); + mtdcr(cntrl0, cntrl0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); /* set output pins to high */ - out32(GPIO0_OR, CFG_EEPROM_WP); + out32(GPIO0_OR, CONFIG_SYS_EEPROM_WP); /* setup for output (LED=off) */ - out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); + out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -108,7 +108,7 @@ int checkboard (void) return 0; } -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. * -1: deliver current state * 0: disable write @@ -118,23 +118,23 @@ int checkboard (void) * 0/1: current state if was -1. */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -142,7 +142,7 @@ int eeprom_write_enable (unsigned dev_addr, int state) { } #endif -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int query = argc == 1; @@ -150,21 +150,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -179,4 +179,4 @@ U_BOOT_CMD( "eepwren - Enable / disable / query EEPROM write access\n", NULL ); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c index de847f9beac..56c822ec97f 100644 --- a/board/esd/cpci2dp/flash.c +++ b/board/esd/cpci2dp/flash.c @@ -47,7 +47,7 @@ unsigned long flash_init (void) unsigned long base_b0; /* Init: no FLASHes known */ - for (i=0; i= 2) { - volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1; + volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1; - if (*fpga_status & CFG_FPGA_STATUS_FLASH) { + if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) { puts ("FLASH Bank B, "); } else { puts ("FLASH Bank A, "); @@ -504,15 +504,15 @@ void reset_phy(void) void ide_set_reset(int on) { - volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; + volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_MODE_CF_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET; } } @@ -555,12 +555,12 @@ int pci_pre_init(struct pci_controller *hose) #ifdef CONFIG_CPCI405AB -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ - |= CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ - &= ~CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ - & CFG_FPGA_MODE_1WIRE) +#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ + |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR) +#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ + &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) +#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \ + & CONFIG_SYS_FPGA_MODE_1WIRE) /* * Generate a 1-wire reset, return 1 if no presence detect was found, @@ -690,7 +690,7 @@ U_BOOT_CMD( NULL ); -#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ /* @@ -706,7 +706,7 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) IPaddr_t ipaddr; buf = malloc(CONFIG_ENV_SIZE_2); - if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { puts("\nError reading backplane EEPROM!\n"); } else { crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); @@ -771,7 +771,7 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); *(ulong *)buf = crc; - if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { + if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { puts("\nError writing backplane EEPROM!\n"); } diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index e766895bb06..d535924f86f 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -66,7 +66,7 @@ unsigned long flash_init (void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index 2a42e65de0d..6eedb83ff15 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -81,7 +81,7 @@ static void sdram_start(int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -106,9 +106,9 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); @@ -144,9 +144,9 @@ phys_size_t initdram(int board_type) #if 0 /* find RAM size using SDRAM CS1 only */ sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(0); #endif /* set SDRAM CS1 size according to the amount of RAM found */ @@ -180,10 +180,10 @@ void flash_afterinit(ulong size) /* adjust mapping */ *(vu_long *) MPC5XXX_BOOTCS_START = *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *) MPC5XXX_BOOTCS_STOP = *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c index d76af02dbef..9b578b5f5ec 100644 --- a/board/esd/cpci5200/strataflash.c +++ b/board/esd/cpci5200/strataflash.c @@ -102,7 +102,7 @@ typedef union { #define NUM_ERASE_REGIONS 4 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -121,7 +121,7 @@ static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword); static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char *prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); #endif @@ -185,14 +185,14 @@ unsigned long flash_init(void) * */ - address = CFG_FLASH_BASE; + address = CONFIG_SYS_FLASH_BASE; size = 0; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; + address += CONFIG_SYS_FLASH_INCREMENT; if (flash_info[i].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", @@ -202,9 +202,9 @@ unsigned long flash_init(void) #if 0 /* test-only */ /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) for (i = 0; - flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1; + flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1; i++) (void)flash_real_protect(&flash_info[0], i, 1); #endif @@ -326,7 +326,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) return rc; wp = cp; } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE while (cnt >= info->portwidth) { i = info->buffer_size > cnt ? cnt : info->buffer_size; if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK) @@ -347,7 +347,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) wp += info->portwidth; cnt -= info->portwidth; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); } @@ -727,7 +727,7 @@ static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) return flash_full_status_check(info, 0, info->write_tout, "write"); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* loop through the sectors from the highest address * when the passed address is greater or equal to the sector address @@ -801,4 +801,4 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 5ab76c6b872..70bae60c68d 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -125,7 +125,7 @@ extern flash_info_t flash_info[]; /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -134,7 +134,7 @@ extern flash_info_t flash_info[]; */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -197,7 +197,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ @@ -206,7 +206,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -224,21 +224,21 @@ static void gt_pci_config (void) /* ronen- add write to pci remap registers for 64460. in 64360 when writing to pci base go and overide remap automaticaly, in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -254,7 +254,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -270,7 +270,7 @@ static void gt_cpu_config (void) tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif @@ -320,7 +320,7 @@ int board_early_init_f (void) * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); /* No PCI in first release of Port To_do: enable it. */ #ifdef CONFIG_PCI @@ -364,45 +364,45 @@ int board_early_init_f (void) * registers to boot from the sram. (device0) */ - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR); + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR); -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ /* detect if we are booting from the 32 bit flash */ if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); + CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ #endif gt_cpu_config (); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); DEBUG_LED0_ON (); DEBUG_LED1_ON (); DEBUG_LED2_ON (); @@ -415,7 +415,7 @@ int board_early_init_f (void) int misc_init_r () { icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -428,19 +428,19 @@ int misc_init_r () /* disable the dcache and MMU */ dcache_lock (); #endif - if (flash_info[3].size < CFG_FLASH_INCREMENT) { + if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) { unsigned int flash_offset; unsigned int l; - flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size; - for (l = 0; l < CFG_MAX_FLASH_SECT; l++) { + flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size; + for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) { if (flash_info[3].start[l] != 0) { flash_info[3].start[l] += flash_offset; } } flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[3]); } return 0; @@ -449,7 +449,7 @@ int misc_init_r () void after_reloc (ulong dest_addr, gd_t * gd) { - memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); display_mem_map (); /* now, jump to the main ppcboot board init code */ @@ -469,7 +469,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -540,7 +540,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -571,7 +571,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaLL, @@ -634,7 +634,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -661,9 +661,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -688,8 +688,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -706,9 +706,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -766,7 +766,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -798,8 +798,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -865,23 +865,23 @@ int testdram (void) int runaddress = 0; int runwalk = 0; -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA s = getenv ("testdramdata"); rundata = (s && (*s == 'y')) ? 1 : 0; #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS s = getenv ("testdramaddress"); runaddress = (s && (*s == 'y')) ? 1 : 0; #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK s = getenv ("testdramwalk"); runwalk = (s && (*s == 'y')) ? 1 : 0; #endif if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -891,7 +891,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -901,7 +901,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -917,7 +917,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ @@ -956,7 +956,7 @@ void board_prebootm_init () /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */ /* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS); + my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS); icache_disable (); dcache_disable (); diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c index 5b1bc01c21e..d95567f7df9 100644 --- a/board/esd/cpci750/i2c.c +++ b/board/esd/cpci750/i2c.c @@ -46,7 +46,7 @@ static void i2c_init (int speed, int slaveaddr) unsigned int n, m, freq, margin, power; unsigned int actualN = 0, actualM = 0; unsigned int minMargin = 0xffffffff; - unsigned int tclk = CFG_TCLK; + unsigned int tclk = CONFIG_SYS_TCLK; unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ DP (puts ("i2c_init\n")); @@ -380,7 +380,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_read\n")); @@ -428,7 +428,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_write\n")); @@ -464,7 +464,7 @@ int i2c_probe (uchar chip) unsigned int i2c_status; #endif uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_probe\n")); diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 0adafe2d085..9bdc5234534 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -30,7 +30,7 @@ #include #include -extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; +extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; int ide_preinit (void) { @@ -39,7 +39,7 @@ int ide_preinit (void) int l; status = 1; - for (l = 0; l < CFG_IDE_MAXBUS; l++) { + for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1103, 0x0004, 0); @@ -51,11 +51,11 @@ int ide_preinit (void) pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, (u32 *) & ide_bus_offset[0]); ide_bus_offset[0] &= 0xfffffffe; - ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE; pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, (u32 *) & ide_bus_offset[1]); ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; } return (status); } diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h index bca0e1ff506..de3758a5136 100644 --- a/board/esd/cpci750/local.h +++ b/board/esd/cpci750/local.h @@ -48,7 +48,7 @@ /* #define CONFIG_BOOTCOMMAND */ /* #define CONFIG_RAMBOOTCOMMAND */ /* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CFG_AUTOLOAD */ +/* #define CONFIG_SYS_AUTOLOAD */ /* #define CONFIG_PREBOOT */ /* These don't */ diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S index 160b1d31f76..233fd83bcca 100644 --- a/board/esd/cpci750/misc.S +++ b/board/esd/cpci750/misc.S @@ -16,7 +16,7 @@ board_relocate_rom: mflr r7 /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h + lis r11, CONFIG_SYS_GT_REGS@h /* if we're using ECC, we must use the DMA engine to copy ourselves */ bl start_idma_transfer_0 bl wait_for_idma_0 @@ -29,12 +29,12 @@ board_relocate_rom: board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ /* now that we're running from ram, init the rest of main memory * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l + lis r8, CONFIG_SYS_MONITOR_LEN@h + ori r8, r8, CONFIG_SYS_MONITOR_LEN@l divw r3, r10, r8 @@ -120,15 +120,15 @@ stop_idma_engine_0: blr #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* NOTE: trashes r3-r7 */ .globl board_asm_init board_asm_init: /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r3, CONFIG_SYS_DFL_GT_REGS@h + ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTERNAL_SPACE_DECODE /* test to see if we've already moved */ @@ -153,11 +153,11 @@ board_asm_init: cmp cr0, r7, r6 bne 1b - lis r3, CFG_INT_SRAM_BASE@h - ori r3, r3, CFG_INT_SRAM_BASE@l + lis r3, CONFIG_SYS_INT_SRAM_BASE@h + ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l rlwinm r3, r3, 16, 16, 31 - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTEGRATED_SRAM_BASE_ADDR stwbrx r3, r5, r4 diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c index fa8d3bda964..c89426d0858 100644 --- a/board/esd/cpci750/mpsc.c +++ b/board/esd/cpci750/mpsc.c @@ -427,7 +427,7 @@ void mpsc_sdma_init (void) (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -517,9 +517,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index c335ebf0bf8..cbe766ffd23 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -932,14 +932,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -981,14 +981,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 0291937e0b3..4c03630fb57 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -350,7 +350,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT +#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT for (i = 0; i <= 127; i++) { printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], @@ -1656,13 +1656,13 @@ initdram(int board_type) if (dimmInfo2.numOfModuleBanks > 2) printf("Error, SPD claims DIMM2 has >2 banks\n"); - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (! checkbank[bank_no]) continue; - if ((total + check) > CFG_GT_REGS) - check = CFG_GT_REGS - total; + if ((total + check) > CONFIG_SYS_GT_REGS) + check = CONFIG_SYS_GT_REGS - total; memory_map_bank(bank_no, total, check); realsize = dram_size((long int *)total, check); diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c index de847f9beac..56c822ec97f 100644 --- a/board/esd/cpciiser4/flash.c +++ b/board/esd/cpciiser4/flash.c @@ -47,7 +47,7 @@ unsigned long flash_init (void) unsigned long base_b0; /* Init: no FLASHes known */ - for (i=0; i> (28 + CFG_NAND0_CS)) | - (0x80000000 >> (28 + CFG_NAND1_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) | + (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); return 0; @@ -273,7 +273,7 @@ int misc_init_r(void) * We have to wait at least 560ms until we may call usbhub_init */ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | - CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N); + CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N); /* * flash USR1/2 LEDs (600ms) @@ -282,22 +282,22 @@ int misc_init_r(void) */ for (j = 0; j < 3; j++) { out_be32((void*)GPIO1_OR, - (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) | - CFG_GPIO1_LEDUSR1); + (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) | + CONFIG_SYS_GPIO1_LEDUSR1); for (i = 0; i < 100; i++) udelay(1000); out_be32((void*)GPIO1_OR, - (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) | - CFG_GPIO1_LEDUSR2); + (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) | + CONFIG_SYS_GPIO1_LEDUSR2); for (i = 0; i < 100; i++) udelay(1000); } out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & - ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2)); + ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2)); if (usbhub_init()) du440_post_errors++; @@ -310,14 +310,14 @@ int misc_init_r(void) int pld_revision(void) { - out8(CFG_CPLD_BASE, 0x00); - return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK); + out8(CONFIG_SYS_CPLD_BASE, 0x00); + return (int)(in8(CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK); } int board_revision(void) { - int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK) - >> CFG_GPIO1_HWVER_SHIFT); + int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK) + >> CONFIG_SYS_GPIO1_HWVER_SHIFT); return ((rpins & 1) << 3) | ((rpins & 2) << 1) | ((rpins & 4) >> 1) | ((rpins & 8) >> 3); @@ -328,7 +328,7 @@ void board_show_activity (ulong timestamp) { if ((timestamp % 100) == 0) out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1); + in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1); } void show_activity(int arg) @@ -421,7 +421,7 @@ int pci_pre_init(struct pci_controller *hose) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /* @@ -437,16 +437,16 @@ void pci_target_init(struct pci_controller *hose) */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ @@ -479,9 +479,9 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -496,7 +496,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /* * is_pci_host @@ -524,18 +524,18 @@ int last_stage_init(void) int e, i; /* everyting is ok: turn on POST-LED */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST); + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); /* slowly blink on errors and finally keep LED off */ for (e = 0; e < du440_post_errors; e++) { out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST); + in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); for (i = 0; i < 500; i++) udelay(1000); out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST); + in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST); for (i = 0; i < 500; i++) udelay(1000); @@ -583,9 +583,9 @@ int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("ERROR - no signal\n"); t1 = t2 = 0; - pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77; + pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; while (!ctrlc()) { - pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77; + pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; if (pin && !pinold) { /* bit start */ t1 = get_ticks(); if (t2 && ((unsigned int)(t1 - t2) / @@ -661,7 +661,7 @@ U_BOOT_CMD( ); #endif /* CONFIG_I2C_MULTI_BUS */ -#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 int boot_eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, @@ -671,7 +671,7 @@ int boot_eeprom_write (unsigned dev_addr, unsigned blk_off; int rcode = 0; -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 1); #endif /* @@ -700,9 +700,9 @@ int boot_eeprom_write (unsigned dev_addr, * bytes that can be ccessed with the single read or write * operation. */ -#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) -#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) maxlen = BOOT_EEPROM_PAGE_SIZE - @@ -722,11 +722,11 @@ int boot_eeprom_write (unsigned dev_addr, buffer += len; offset += len; -#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif } -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 0); #endif return rcode; @@ -779,7 +779,7 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf("Writing boot EEPROM ...\n"); - if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR, + if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0, (uchar*)sdsdp, 16) != 0) printf("boot_eeprom_write failed\n"); else @@ -793,7 +793,7 @@ U_BOOT_CMD( NULL ); -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* * Input: I2C address of EEPROM device to enable. * -1: deliver current state @@ -805,27 +805,27 @@ U_BOOT_CMD( */ int eeprom_write_enable (unsigned dev_addr, int state) { - if ((CFG_I2C_EEPROM_ADDR != dev_addr) && - (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) + if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && + (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) return -1; else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP); state = 0; break; default: /* Read current status back. */ state = (0 == (in_be32((void*)GPIO0_OR) & - CFG_GPIO0_EP_EEP)); + CONFIG_SYS_GPIO0_EP_EEP)); break; } } @@ -839,21 +839,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) puts ("Query of write access state failed.\n"); else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) puts ("Setup of write access state failed.\n"); @@ -865,19 +865,19 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ static int got_pldirq; static int pld_interrupt(u32 arg) { int rc = -1; /* not for us */ - u8 status = in8(CFG_CPLD_BASE); + u8 status = in8(CONFIG_SYS_CPLD_BASE); /* check for PLD interrupt */ if (status & PWR_INT_FLAG) { /* reset this int */ - out8(CFG_CPLD_BASE, 0); + out8(CONFIG_SYS_CPLD_BASE, 0); rc = 0; got_pldirq = 1; /* trigger backend */ } @@ -890,7 +890,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) got_pldirq = 0; /* clear any pending interrupt */ - out8(CFG_CPLD_BASE, 0); + out8(CONFIG_SYS_CPLD_BASE, 0); irq_install_handler(CPLD_IRQ, (interrupt_handler_t *)pld_interrupt, 0); @@ -906,7 +906,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (got_pldirq) { printf("Got interrupt!\n"); printf("Power %sready!\n", - in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT "); + in8(CONFIG_SYS_CPLD_BASE) & PWR_RDY ? "":"NOT "); } irq_free_handler(CPLD_IRQ); @@ -970,7 +970,7 @@ U_BOOT_CMD( int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { unsigned long long start, end; - char c, cmd[CFG_CBSIZE]; + char c, cmd[CONFIG_SYS_CBSIZE]; char *p, *d = cmd; int ret, i; ulong us; @@ -998,7 +998,7 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return ret; } U_BOOT_CMD( - time, CFG_MAXARGS, 1, do_time, + time, CONFIG_SYS_MAXARGS, 1, do_time, "time - run command and output execution time\n", NULL ); @@ -1048,7 +1048,7 @@ int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } U_BOOT_CMD( - gfxdemo, CFG_MAXARGS, 1, do_gfxdemo, + gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo, "gfxdemo - demo\n", NULL ); diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h index 83fdac7c63f..a124a7ee9b5 100644 --- a/board/esd/du440/du440.h +++ b/board/esd/du440/du440.h @@ -20,18 +20,18 @@ #define SDR0_USB0 0x0320 /* USB Control Register */ -#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */ -#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */ +#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */ +#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */ -#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */ -#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */ +#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */ +#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */ -#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */ -#define CFG_GPIO1_HWVER_SHIFT 4 -#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */ -#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */ -#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */ -#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */ +#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */ +#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4 +#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */ +#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */ +#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */ +#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */ #define CPLD_VERSION_MASK 0x0f #define PWR_INT_FLAG 0x80 diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S index 4390b507448..3cac6b11bb0 100644 --- a/board/esd/du440/init.S +++ b/board/esd/du440/init.S @@ -44,30 +44,30 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for PCI IO */ - tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entries for EBC: CPLD, DUMEM, DUIO */ - tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for NAND */ - tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds index b20fb1c0a28..3cfec834e2d 100644 --- a/board/esd/du440/u-boot.lds +++ b/board/esd/du440/u-boot.lds @@ -137,7 +137,7 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c index 89af1190a8a..274ada9fe5c 100644 --- a/board/esd/hh405/flash.c +++ b/board/esd/hh405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; iboard_type >= 2) { - if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) { - if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) { - *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN; + if (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT) { + if (!(*fpga_ctrl & CONFIG_SYS_FPGA_CTRL_CF_BUS_EN)) { + *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN; for (i=0; i<300; i++) udelay(1000); - *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; for (i=0; i<20; i++) udelay(1000); } } else { - *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN; - *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN; + *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_PWRN; } } @@ -392,11 +392,11 @@ int cf_enable(void) int misc_init_r (void) { volatile unsigned short *fpga_ctrl = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); volatile unsigned short *lcd_contrast = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4); volatile unsigned short *lcd_backlight = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6); unsigned char *dst; ulong len = sizeof(fpgadata); int status; @@ -405,8 +405,8 @@ int misc_init_r (void) char *str; unsigned long contrast0 = 0xffffffff; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -474,22 +474,22 @@ int misc_init_r (void) /* * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); /* * Reset touch-screen controller */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); udelay(1000); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_TOUCH_RST); /* * Enable power on PS/2 interface (with reset) */ - *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR); + *fpga_ctrl &= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR); for (i=0;i<500;i++) udelay(1000); - *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR); + *fpga_ctrl |= (CONFIG_SYS_FPGA_CTRL_PS2_PWR); /* * Get contrast value from environment variable @@ -512,11 +512,11 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL; *lcd_backlight = 0x0000; lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_1024_768_8bpp, sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]), logo_bmp_1024, sizeof(logo_bmp_1024)); @@ -524,11 +524,11 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL; + *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL; *lcd_backlight = 0x0000; lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), logo_bmp_640, sizeof(logo_bmp_640)); @@ -545,7 +545,7 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; /* * Set lcd clock (small epson) */ @@ -553,7 +553,7 @@ int misc_init_r (void) udelay(100); /* wait for 100 us */ lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13705_320_240_8bpp, sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]), logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp)); @@ -570,14 +570,14 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; /* * Set lcd clock (small epson), enable 1-wire interface */ - *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE; + *fpga_ctrl |= LCD_CLK_08330 | CONFIG_SYS_FPGA_CTRL_OW_ENABLE; lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); @@ -647,27 +647,27 @@ int checkboard (void) void ide_set_reset(int on) { volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); volatile unsigned short *fpga_status = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2); - if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) || + if (((gd->board_type >= 2) && (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT)) || (gd->board_type < 2)) { /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ cf_enable(); - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; } } } #endif /* CONFIG_IDE_RESET */ -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. * -1: deliver current state * 0: disable write @@ -678,23 +678,23 @@ void ide_set_reset(int on) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -708,21 +708,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -735,7 +735,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ #ifdef CONFIG_VIDEO_SM501 diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c index 89af1190a8a..274ada9fe5c 100644 --- a/board/esd/hub405/flash.c +++ b/board/esd/hub405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i test2) { sdram_start(0); @@ -143,9 +143,9 @@ phys_size_t initdram(int board_type) #if 0 /* find RAM size using SDRAM CS1 only */ sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(0); #endif /* set SDRAM CS1 size according to the amount of RAM found */ @@ -175,14 +175,14 @@ void flash_preinit(void) void flash_afterinit(ulong size) { - if (size == CFG_FLASH_SIZE) { + if (size == CONFIG_SYS_FLASH_SIZE) { /* adjust mapping */ *(vu_long *) MPC5XXX_BOOTCS_START = *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *) MPC5XXX_BOOTCS_STOP = *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c index c3d8bec9137..e763a895ea4 100644 --- a/board/esd/ocrtc/flash.c +++ b/board/esd/ocrtc/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c index 3b21781d7df..90584838008 100644 --- a/board/esd/pci405/flash.c +++ b/board/esd/pci405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ typedef unsigned short FLASH_PORT_WIDTH; typedef volatile unsigned short FLASH_PORT_WIDTHV; @@ -60,7 +60,7 @@ unsigned long flash_init(void) extern void flash_preinit(void); extern void flash_afterinit(uint, ulong, ulong); - ulong flashbase = CFG_FLASH_BASE; + ulong flashbase = CONFIG_SYS_FLASH_BASE; flash_preinit(); @@ -69,11 +69,11 @@ unsigned long flash_init(void) flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]); size += flash_info[i].size; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); + flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif #ifdef CONFIG_ENV_IS_IN_FLASH @@ -107,14 +107,14 @@ static flash_info_t *flash_get_info(ulong base) { int i; flash_info_t *info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { info = &flash_info[i]; if ((info->size) && (info->start[0] <= base) && (base <= info->start[0] + info->size - 1)) { break; } } - return (i == CFG_MAX_FLASH_BANKS ? 0 : info); + return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info); } /*----------------------------------------------------------------------- @@ -336,7 +336,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { udelay(1000); while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); if (intel) { /* suspend erase */ @@ -347,14 +347,14 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { break; } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc('.'); last = get_timer(0); } } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc('.'); last = get_timer(0); @@ -452,7 +452,7 @@ static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) { /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ res = 1; } diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index c4c0221d02f..f7962afa5c3 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -81,7 +81,7 @@ static void sdram_start(int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -106,9 +106,9 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); @@ -144,9 +144,9 @@ phys_size_t initdram(int board_type) #if 0 /* find RAM size using SDRAM CS1 only */ sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(0); #endif /* set SDRAM CS1 size according to the amount of RAM found */ @@ -180,10 +180,10 @@ void flash_afterinit(ulong size) /* adjust mapping */ *(vu_long *) MPC5XXX_BOOTCS_START = *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *) MPC5XXX_BOOTCS_STOP = *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } @@ -258,10 +258,10 @@ void init_power_switch(void) *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; __asm__ volatile ("sync"); } - *(vu_char *) CFG_CS1_START = 0x02; /* Red Power LED on */ + *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */ __asm__ volatile ("sync"); - *(vu_char *) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */ + *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */ __asm__ volatile ("sync"); } diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c index 89af1190a8a..274ada9fe5c 100644 --- a/board/esd/plu405/flash.c +++ b/board/esd/plu405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; ibd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -179,23 +179,23 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); udelay(10); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); udelay(1000); /* * Set NAND-FLASH GPIO signals to default */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); + in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); /* * Setup EEPROM write protection */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); /* * Enable interrupts in exar duart mcr[3] @@ -230,15 +230,15 @@ int checkboard (void) void ide_set_reset(int on) { volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; } } #endif /* CONFIG_IDE_RESET */ @@ -254,7 +254,7 @@ void reset_phy(void) #endif } -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. * -1: deliver current state * 0: disable write @@ -265,26 +265,26 @@ void reset_phy(void) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO0. */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO0. */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ state = (0 == (in_be32((void*)GPIO0_OR) & - CFG_EEPROM_WP)); + CONFIG_SYS_EEPROM_WP)); break; } } @@ -298,21 +298,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -325,4 +325,4 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 90a212b8c43..c0781dc950e 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -72,23 +72,23 @@ int board_early_init_f (void) * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \ - CFG_FPGA_DONE | \ - CFG_XEREADY | \ - CFG_NONMONARCH | \ - CFG_REV1_2) << 5)); + mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \ + CONFIG_SYS_FPGA_DONE | \ + CONFIG_SYS_XEREADY | \ + CONFIG_SYS_NONMONARCH | \ + CONFIG_SYS_REV1_2) << 5)); - if (!(in32(GPIO0_IR) & CFG_REV1_2)) { + if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) { /* rev 1.2 boards */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \ - CFG_SELF_RST) << 5)); + mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \ + CONFIG_SYS_SELF_RST) << 5)); } out32(GPIO0_OR, 0); - out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */ + out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */ /* - check if rev1_2 is low, then: - * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST# + * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST# */ return 0; @@ -104,7 +104,7 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */ + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */ return (0); } @@ -112,13 +112,13 @@ ushort pmc405_pci_subsys_deviceid(void) { ulong val; val = in32(GPIO0_IR); - if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ - if (val & CFG_NONMONARCH) { /* monarch# signal */ - return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; + if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ + if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ + return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; } - return CFG_PCI_SUBSYS_DEVICEID_MONARCH; + return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH; } - return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; + return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; } /* @@ -140,9 +140,9 @@ int checkboard (void) } val = in32(GPIO0_IR); - if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ puts(" rev1.2 ("); - if (val & CFG_NONMONARCH) { /* monarch# signal */ + if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ puts("non-"); } puts("monarch)"); diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 74cf4c3e15b..38ee74eb4bc 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -323,7 +323,7 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] } printf("Writing boot EEPROM ...\n"); - if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR, + if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0, (uchar*)sdsdp, count) != 0) printf("bootstrap_eeprom_write failed\n"); else @@ -513,7 +513,7 @@ U_BOOT_CMD( " (pciaddr will be aligned to 256MB)\n" ); -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int query = argc == 1; @@ -521,21 +521,21 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts("Query of write access state failed.\n"); } else { printf("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts("Setup of write access state failed.\n"); @@ -547,6 +547,6 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ #endif /* CONFIG_CMD_BSP */ diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk index e62b8d30e41..0c4d58282e7 100644 --- a/board/esd/pmc440/config.mk +++ b/board/esd/pmc440/config.mk @@ -37,5 +37,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index 148af71bb53..26a8282cec0 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -44,28 +44,28 @@ tlbtab: * speed up boot process. It is patched after relocation to enable SA_I */ #ifndef CONFIG_NAND_SPL - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) #else - tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for DDR SDRAM (Up to 2GB) */ #ifdef CONFIG_4xx_DCACHE - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) #else - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) #endif -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entries for EBC */ /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral @@ -76,7 +76,7 @@ tlbtab: tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for NAND */ - tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) @@ -98,8 +98,8 @@ tlbtab: * For NAND booting the first TLB has to be reconfigured to full size * and with caching disabled after running from RAM! */ -#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) .globl reconfig_tlb0 diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 85ef26f67be..013815e2659 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size(ulong base, int banknum); int pci_is_66mhz(void); @@ -71,7 +71,7 @@ struct serial_device *default_serial_console(void) /* mark scratchreg valid */ scratchreg = (scratchreg & 0xffffff00) | 0x80; - i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, + i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { scratchreg |= buf[2]; @@ -103,7 +103,7 @@ int board_early_init_f(void) /* * Setup the GPIO pins - * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file + * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file */ out32(GPIO0_OR, 0x40000002); out32(GPIO0_TCR, 0x4c90011f); @@ -190,7 +190,7 @@ int board_early_init_f(void) SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CFG_NAND_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); return 0; @@ -242,7 +242,7 @@ int misc_init_r(void) #ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); @@ -498,7 +498,7 @@ int pci_pre_init(struct pci_controller *hose) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { char *ptmla_str, *ptmms_str; @@ -516,8 +516,8 @@ void pci_target_init(struct pci_controller *hose) */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ /* and enable region */ @@ -563,7 +563,7 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); /* disabled for PMC405 backward compatibility */ /* Configure command register as bus master */ @@ -581,9 +581,9 @@ void pci_target_init(struct pci_controller *hose) if (!is_monarch()) { /* Program the board's subsystem id/classcode */ pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CFG_PCI_SUBSYS_ID_NONMONARCH); + CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CFG_PCI_CLASSCODE_NONMONARCH); + CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); /* PCI configuration done: release ERREADY */ out_be32((void*)GPIO1_OR, @@ -593,17 +593,17 @@ void pci_target_init(struct pci_controller *hose) } else { /* Program the board's subsystem id/classcode */ pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CFG_PCI_SUBSYS_ID_MONARCH); + CONFIG_SYS_PCI_SUBSYS_ID_MONARCH); pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CFG_PCI_CLASSCODE_MONARCH); + CONFIG_SYS_PCI_CLASSCODE_MONARCH); } } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /* * pci_master_init */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -620,7 +620,7 @@ void pci_master_init(struct pci_controller *hose) PCI_COMMAND_MEMORY); } } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ static void wait_for_pci_ready(void) { @@ -708,7 +708,7 @@ void reset_phy(void) } #endif -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* * Input: I2C address of EEPROM device to enable. * -1: deliver current state @@ -720,8 +720,8 @@ void reset_phy(void) */ int eeprom_write_enable(unsigned dev_addr, int state) { - if ((CFG_I2C_EEPROM_ADDR != dev_addr) && - (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) { + if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && + (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) { return -1; } else { switch (state) { @@ -743,9 +743,9 @@ int eeprom_write_enable(unsigned dev_addr, int state) } return state; } -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ -#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) { @@ -753,7 +753,7 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, unsigned blk_off; int rcode = 0; -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 1); #endif /* @@ -776,7 +776,7 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, len = end - offset; -#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) maxlen = BOOT_EEPROM_PAGE_SIZE - @@ -793,11 +793,11 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, buffer += len; offset += len; -#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif } -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 0); #endif return rcode; @@ -845,7 +845,7 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, return rcode; } -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) int usb_board_init(void) { char *act = getenv("usbact"); @@ -875,4 +875,4 @@ int usb_board_init_fail(void) usb_board_stop(); return 0; } -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h index 7e70fd1cb70..d834f258571 100644 --- a/board/esd/pmc440/pmc440.h +++ b/board/esd/pmc440/pmc440.h @@ -54,7 +54,7 @@ /*----------------------------------------------------------------------- * FPGA interface */ -#define FPGA_BA CFG_FPGA_BASE0 +#define FPGA_BA CONFIG_SYS_FPGA_BASE0 #define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v)) #define FPGA_IN32(p) in_be32((void*)(p)) #define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v)) @@ -134,7 +134,7 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define HOSTCTRL_HCINT_GATE (1 << 1) #define HOSTCTRL_HCINT_FLAG (1 << 0) -#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000) +#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000) #define NGCC_CTRL_FPGARST_N (1 << 2) /*----------------------------------------------------------------------- diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index c7294c99459..197857ad097 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -111,5 +111,5 @@ phys_size_t initdram (int board_type) */ set_mcsr(get_mcsr()); - return (CFG_MBYTES_SDRAM << 20); + return (CONFIG_SYS_MBYTES_SDRAM << 20); } diff --git a/board/esd/pmc440/u-boot.lds b/board/esd/pmc440/u-boot.lds index b20fb1c0a28..3cfec834e2d 100644 --- a/board/esd/pmc440/u-boot.lds +++ b/board/esd/pmc440/u-boot.lds @@ -137,7 +137,7 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c index 13c07d2d33f..ce905e94c0e 100644 --- a/board/esd/tasreg/flash.c +++ b/board/esd/tasreg/flash.c @@ -45,13 +45,13 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i I2C address of EEPROM device to enable. * -1: deliver current state * 0: disable write @@ -337,23 +337,23 @@ void reset_phy(void) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -367,21 +367,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -394,4 +394,4 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c index 89af1190a8a..274ada9fe5c 100644 --- a/board/esd/vom405/flash.c +++ b/board/esd/vom405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i