From 9cccc358c4a2f539746bc98c741e714cc7d9b5d2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 23 Aug 2022 19:27:08 +0200 Subject: ARM: stm32: Switch DHSOM to FMC2 EBI driver Perform long overdue conversion of ad-hoc FMC2 EBI bus initialization to upstream FMC2 EBI driver. No functional change. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/dhelectronics/dh_stm32mp1/board.c | 52 --------------------------------- 1 file changed, 52 deletions(-) (limited to 'board/dhelectronics') diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index e3c7ed1049..9188f5381e 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -527,56 +527,6 @@ static void sysconf_init(void) #endif } -static void board_init_fmc2(void) -{ -#define STM32_FMC2_BCR1 0x0 -#define STM32_FMC2_BTR1 0x4 -#define STM32_FMC2_BWTR1 0x104 -#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1) -#define STM32_FMC2_BCRx_FMCEN BIT(31) -#define STM32_FMC2_BCRx_WREN BIT(12) -#define STM32_FMC2_BCRx_RSVD BIT(7) -#define STM32_FMC2_BCRx_FACCEN BIT(6) -#define STM32_FMC2_BCRx_MWID(n) ((n) << 4) -#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2) -#define STM32_FMC2_BCRx_MUXEN BIT(1) -#define STM32_FMC2_BCRx_MBKEN BIT(0) -#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1) -#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30) -#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16) -#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8) -#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4) -#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0) - -#define RCC_MP_AHB6RSTCLRR 0x218 -#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12) -#define RCC_MP_AHB6ENSETR 0x19c -#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) - - const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD | - STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) | - STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN | - STM32_FMC2_BCRx_MBKEN; - const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) | - STM32_FMC2_BTRx_BUSTURN(2) | - STM32_FMC2_BTRx_DATAST(0x22) | - STM32_FMC2_BTRx_ADDHLD(2) | - STM32_FMC2_BTRx_ADDSET(2); - - /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */ - writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR); - writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR); - - /* KS8851-16MLL -- Muxed mode */ - writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1)); - writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1)); - /* AS7C34098 SRAM on X11 -- Muxed mode */ - writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3)); - writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3)); - - setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN); -} - #ifdef CONFIG_DM_REGULATOR #define STPMIC_NVM_BUCKS_VOUT_SHR 0xfc #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 0 @@ -671,8 +621,6 @@ int board_init(void) sysconf_init(); - board_init_fmc2(); - return 0; } -- cgit v1.2.3 From 8ee4ffcd0bf684ade6eccffec796a49ee15b3333 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 19 Aug 2022 13:02:53 +0200 Subject: ARM: imx: Update DDR frequency on i.MX8M Plus DHCOM Commit 99c7cc58e12 ("ddr: imx: Add i.MX9 DDR controller driver") contains an inobvious side-effect which renders all systems using DRAM controller at 3732 MT/s unbootable. The change is located in ddrphy_init_set_dfi_clk(), where the switch case statement entry 3732 changed to entry 3733, so any board with DDR calibration data for 3732 MT/s operations needs to be updated to 3733 MT/s to match the change. Since there is currently only one such board, update the board instead of handling both 3732 and 3733 options in the driver. It is likely the NXP MX8MP RPA update will follow and use the later value too. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Cc: Ye Li Cc: uboot-imx Reviewed-by: Fabio Estevam --- board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'board/dhelectronics') diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c index 2eda4a5956..a4c1b121c2 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c @@ -1799,8 +1799,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 3732mts 1D */ - .drate = 3732, + /* P0 3733mts 1D */ + .drate = 3733, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1820,8 +1820,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 3732mts 2D */ - .drate = 3732, + /* P0 3733mts 2D */ + .drate = 3733, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1840,5 +1840,5 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3732, 400, 100, }, + .fsp_table = { 3733, 400, 100, }, }; -- cgit v1.2.3