From 0d4a779ec856fbbac234ea7ae4f751fdbd9bb603 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Mon, 17 Jun 2013 14:23:01 -0700 Subject: Initial addition of Boundary H board Only enable one display (1024x600) Signed-off-by: Robert Winkler --- board/boundary/h/6x_bootscript.txt | 19 + board/boundary/h/6x_bootscript_android.txt | 28 ++ board/boundary/h/6x_upgrade.txt | 45 ++ board/boundary/h/Makefile | 41 ++ board/boundary/h/h.c | 744 +++++++++++++++++++++++++++++ board/boundary/h/hquad2g.cfg | 45 ++ board/boundary/h/hsolo1g.cfg | 45 ++ 7 files changed, 967 insertions(+) create mode 100644 board/boundary/h/6x_bootscript.txt create mode 100644 board/boundary/h/6x_bootscript_android.txt create mode 100644 board/boundary/h/6x_upgrade.txt create mode 100644 board/boundary/h/Makefile create mode 100644 board/boundary/h/h.c create mode 100644 board/boundary/h/hquad2g.cfg create mode 100644 board/boundary/h/hsolo1g.cfg (limited to 'board/boundary') diff --git a/board/boundary/h/6x_bootscript.txt b/board/boundary/h/6x_bootscript.txt new file mode 100644 index 00000000000..3d6c434fd1a --- /dev/null +++ b/board/boundary/h/6x_bootscript.txt @@ -0,0 +1,19 @@ +setenv bootargs enable_wait_mode=off ldb=sep0 +setenv nextcon 0; +setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 +setenv nextcon 1 +setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,INNOLUX-WVGA,if=RGB666 +setenv nextcon 2 +setenv fbmem "fbmem=28M,10M"; + +while test "4" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs $fbmem +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 +${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage +&& ${fs}load ${dtype} ${disk}:1 12800000 /boot/uramdisk.img +&& bootm 10800000 12800000 ; +echo "Error loading kernel image" diff --git a/board/boundary/h/6x_bootscript_android.txt b/board/boundary/h/6x_bootscript_android.txt new file mode 100644 index 00000000000..1821efe8015 --- /dev/null +++ b/board/boundary/h/6x_bootscript_android.txt @@ -0,0 +1,28 @@ +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; +setenv bootargs $bootargs calibration tsdev=tsc2004 + +if test -n "$tempfuse" ; then + setenv bootargs $bootargs thermal.fusedata=$tempfuse +fi + +if test xXGA = "x$panel" ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB24 +else + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,OC-VGA,if=RGB24 +fi + +setenv nextcon 1 +setenv fbmem "fbmem=10M"; + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs $fbmem +${fs}load ${dtype} ${disk}:1 10800000 uImage +&& ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img +&& bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/h/6x_upgrade.txt b/board/boundary/h/6x_upgrade.txt new file mode 100644 index 00000000000..0b8db73a147 --- /dev/null +++ b/board/boundary/h/6x_upgrade.txt @@ -0,0 +1,45 @@ +setenv stdout serial,vga +echo "check U-Boot" ; +setenv offset 0x400 +if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx ; then + echo "read $filesize bytes from SD card" ; + if sf probe || sf probe || \ + sf probe 1 27000000 || sf probe 1 27000000 ; then + echo "probed SPI ROM" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + echo "------- U-Boot versions match" ; + else + echo "Need U-Boot upgrade" ; + echo "Program in 5 seconds" ; + for n in 5 4 3 2 1 ; do + echo $n ; + sleep 1 ; + done + echo "erasing" ; + sf erase 0 0xC0000 ; + # two steps to prevent bricking + echo "programming" ; + sf write 0x12000000 $offset $filesize ; + echo "verifying" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + while echo "---- U-Boot upgraded. reset" ; do + sleep 120 + done + else + echo "Read verification error" ; + fi + else + echo "Error re-reading EEPROM" ; + fi + fi + else + echo "Error reading boot loader from EEPROM" ; + fi + else + echo "Error initializing EEPROM" ; + fi ; +else + echo "No U-Boot image found on SD card" ; +fi diff --git a/board/boundary/h/Makefile b/board/boundary/h/Makefile new file mode 100644 index 00000000000..22451824c2f --- /dev/null +++ b/board/boundary/h/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := h.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/boundary/h/h.c b/board/boundary/h/h.c new file mode 100644 index 00000000000..b73b2fde186 --- /dev/null +++ b/board/boundary/h/h.c @@ -0,0 +1,744 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +int dram_init(void) +{ + gd->ram_size = CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__UART1_RXD, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__UART1_TXD, UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_EIM_D26__UART2_TXD, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D27__UART2_RXD, UART_PAD_CTRL), +}; + +#define PC(a) NEW_PAD_CTRL(a, I2C_PAD_CTRL) + +/* I2C1, SGTL5000 */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = PC(MX6_PAD_EIM_D21__I2C1_SCL), + .gpio_mode = PC(MX6_PAD_EIM_D21__GPIO_3_21), + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = PC(MX6_PAD_EIM_D28__I2C1_SDA), + .gpio_mode = PC(MX6_PAD_EIM_D28__GPIO_3_28), + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C3, J15 - RGB connector */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = PC(MX6_PAD_GPIO_5__I2C3_SCL), + .gpio_mode = PC(MX6_PAD_GPIO_5__GPIO_1_5), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = PC(MX6_PAD_GPIO_16__I2C3_SDA), + .gpio_mode = PC(MX6_PAD_GPIO_16__GPIO_7_11), + .gp = IMX_GPIO_NR(7, 11) + } +}; + +#define GP_SD3_CD IMX_GPIO_NR(7, 0) + +iomux_v3_cfg_t const usdhc3_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD3_CLK__USDHC3_CLK, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_CMD__USDHC3_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__USDHC3_DAT0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__USDHC3_DAT1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__USDHC3_DAT2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__USDHC3_DAT3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__GPIO_7_0, NO_PAD_CTRL), /* CD */ +}; + +#define GP_SD4_CD IMX_GPIO_NR(2, 6) + +iomux_v3_cfg_t const usdhc4_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD4_CLK__USDHC4_CLK, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_CMD__USDHC4_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT0__USDHC4_DAT0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT1__USDHC4_DAT1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT2__USDHC4_DAT2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT3__USDHC4_DAT3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_NANDF_D6__GPIO_2_6, NO_PAD_CTRL), /* CD */ +}; + +#define GP_PHY_AD2 IMX_GPIO_NR(6, 30) +#define GP_PHY_MODE0 IMX_GPIO_NR(6, 25) +#define GP_PHY_MODE1 IMX_GPIO_NR(6, 27) +#define GP_PHY_MODE2 IMX_GPIO_NR(6, 28) +#define GP_PHY_MODE3 IMX_GPIO_NR(6, 29) +#define GP_PHY_CLK125 IMX_GPIO_NR(6, 24) +#define GP_PHY_RESET IMX_GPIO_NR(1, 27) + +iomux_v3_cfg_t const enet_pads1[] = { + NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__ENET_RGMII_TXC, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__ENET_RGMII_TD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__ENET_RGMII_TD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__ENET_RGMII_TD2, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__ENET_RGMII_TD3, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__GPIO_6_30, NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__GPIO_6_25, NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__GPIO_6_27, NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__GPIO_6_28, NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__GPIO_6_29, NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__GPIO_6_24, NO_PAD_CTRL), + /* pin 42 PHY nRST */ + NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__GPIO_1_27, NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__ENET_RGMII_RXC, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__ENET_RGMII_RD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__ENET_RGMII_RD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__ENET_RGMII_RD2, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__ENET_RGMII_RD3, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL), +}; + +/* Broadcom bcm4330 pads on nitrogen6x */ +iomux_v3_cfg_t const bcm4330_pads[] = { + NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO_6_7, OUTPUT_40OHM), /* wlan regulator enable */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO_6_14, WEAK_PULLDOWN), /* wlan wake irq */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO_6_15, OUTPUT_40OHM), /* bt regulator enable */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO_6_16, OUTPUT_40OHM), /* bt wake irq */ + NEW_PAD_CTRL(MX6_PAD_NANDF_D2__GPIO_2_2, OUTPUT_40OHM), /* bt wake */ + NEW_PAD_CTRL(MX6_PAD_NANDF_ALE__GPIO_6_8, OUTPUT_40OHM), /* bt reset */ +}; + +#define GP_WL_EN IMX_GPIO_NR(6, 7) /* NANDF_CLE - active high */ +#define GP_WL_WAKE_IRQ IMX_GPIO_NR(6, 14) /* NANDF_CS1 - active low */ +#define GP_WL_BT_REG_EN IMX_GPIO_NR(6, 15) /* NANDF_CS2 - active high */ +#define GP_WL_BT_WAKE_IRQ IMX_GPIO_NR(6, 16) /* NANDF_CS3 - active low */ +#define GP_WL_BT_RESET IMX_GPIO_NR(6, 8) /* NANDF_ALE - active low */ +#define GP_WL_CLK_REQ_IRQ IMX_GPIO_NR(6, 9) /* NANDF_WP_B - active low */ + +static void setup_iomux_enet(void) +{ + gpio_direction_output(GP_PHY_RESET, 0); + gpio_direction_output(GP_PHY_AD2, 1); + gpio_direction_output(GP_PHY_MODE0, 1); + gpio_direction_output(GP_PHY_MODE1, 1); + gpio_direction_output(GP_PHY_MODE2, 1); + gpio_direction_output(GP_PHY_MODE3, 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(GP_PHY_CLK125, 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(GP_PHY_RESET, 1); + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +#define GP_USB_HUB_RESET IMX_GPIO_NR(7, 12) + +iomux_v3_cfg_t const usb_pads[] = { + NEW_PAD_CTRL(MX6_PAD_GPIO_17__GPIO_7_12, WEAK_PULLUP), /* Hub reset */ + NEW_PAD_CTRL(MX6_PAD_GPIO_1__USBOTG_ID, USDHC_PAD_CTRL), /* USBOTG ID pin */ + NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO_3_22, WEAK_PULLUP), /* usbotg power */ + MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC, /* USBOTG OC pin */ + NEW_PAD_CTRL(MX6_PAD_EIM_RW__GPIO_2_26, WEAK_PULLUP), /* Rev1 usb power */ + NEW_PAD_CTRL(MX6_PAD_EIM_D20__GPIO_3_20, WEAK_PULLUP), /* Rev1 usb power */ + NEW_PAD_CTRL(MX6_PAD_EIM_A25__GPIO_5_2, WEAK_PULLUP), /* Rev1 usb power */ +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB hub */ + gpio_direction_output(GP_USB_HUB_RESET, 0); + mdelay(2); + gpio_set_value(GP_USB_HUB_RESET, 1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int gp = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? GP_SD3_CD : GP_SD4_CD; + + gpio_direction_input(gp); + return !gpio_get_value(gp); +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].max_bus_width = 8; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO_3_19, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), +}; + +void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +unsigned short ksz9031_por_cmds[] = { + 0x0205, 0x0, /* RXDn pad skew */ + 0x0206, 0x0, /* TXDn pad skew */ + 0x0208, 0x03ff, /* TXC/RXC pad skew */ + 0x0, 0x0 +}; + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->uid == 0x221610) { + /* ksz9021 */ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + } else { + ksz9031_send_phy_cmds(phydev, ksz9031_por_cmds); + } + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<gpr[2]); + + if (dev->pixfmt != IPU_PIX_FMT_RGB666) + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + else + reg &= ~IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + reg |= 1; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(GP_LVDS0_BACKLIGHT_PWM, 1); + gpio_direction_output(GP_LVDS1_BACKLIGHT_PWM, 0); +} + +static void enable_ldb1(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + + if (dev->pixfmt != IPU_PIX_FMT_RGB666) + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + else + reg &= ~IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + reg |= 4; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(GP_LVDS0_BACKLIGHT_PWM, 0); + gpio_direction_output(GP_LVDS1_BACKLIGHT_PWM, 1); +} + +static struct display_info_t const d_1024x600 = { + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_RGB666, + .enable = enable_ldb0, + .mode = { + .name = "1024x600", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 20408, + .left_margin = 144, + .right_margin = 40, + .upper_margin = 3, + .lower_margin = 11, + .hsync_len = 104, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } +}; +static struct display_info_t const d_innolux_wvga = { + .bus = 2, + .addr = 0x48, + .pixfmt = IPU_PIX_FMT_RGB666, +// .detect = detect_i2c, + .enable = enable_ldb1, + .mode = { + .name = "INNOLUX-WVGA", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 25000, + .left_margin = 45, + .right_margin = 1056 - 1 - 45 - 800, + .upper_margin = 22, + .lower_margin = 635 - 1 - 22 - 480, + .hsync_len = 1, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + } +}; + +int board_video_skip(void) +{ + int ret; + char const *panel = getenv("panel"); + struct display_info_t const *display = 0; + if (!panel) + panel = "1024x600"; + if (0 == strcmp(panel, "1024x600")) + display = &d_1024x600; + else if (0 == strcmp(panel, "INNOLUX-WVGA")) + display = &d_innolux_wvga; + + if (display) { + ret = ipuv3_fb_init(&display->mode, 0, + display->pixfmt); + if (!ret) { + display->enable(display); + printf("Display: %s (%ux%u)\n", + display->mode.name, + display->mode.xres, + display->mode.yres); + } + enable_rgb(display); + + } else + ret = -EINVAL; + return (0 != ret); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg; + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET + |MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + gpio_direction_input(GP_RGB_BACKLIGHT_PWM); + gpio_direction_input(GP_LVDS0_BACKLIGHT_PWM); + gpio_direction_input(GP_LVDS1_BACKLIGHT_PWM); + gpio_direction_output(GP_RGB_MIRROR_V, 0); + gpio_direction_output(GP_RGB_MIRROR_H, 1); + + gpio_direction_output(GP_LVDS0_12V_5V_BL_SELECT, 0); + gpio_direction_output(GP_RGB_LVDS1_12V_5V_BL_SELECT, 0); + gpio_direction_output(GP_12V_POWER_EN, 0); +} +#endif + +int board_early_init_f(void) +{ + enable_clko1(CLKO1_AHB_CLK_ROOT,7); + + setup_iomux_uart(); + + /* Disable wl1271 */ + gpio_direction_input(GP_WL_WAKE_IRQ); + gpio_direction_input(GP_WL_BT_WAKE_IRQ); + gpio_direction_input(GP_WL_CLK_REQ_IRQ); + gpio_direction_output(GP_WL_EN, 0); + gpio_direction_output(GP_WL_BT_REG_EN, 0); + gpio_direction_output(GP_WL_BT_RESET, 0); + + imx_iomux_v3_setup_multiple_pads(bcm4330_pads, ARRAY_SIZE(bcm4330_pads)); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#define GP_I2C_EN_MIPI IMX_GPIO_NR(2, 16) +#define GP_I2C_EN_LVDS0 IMX_GPIO_NR(2, 21) +#define GP_I2C_EN_LVDS1 IMX_GPIO_NR(2, 22) +#define GP_I2C_EN_RTC IMX_GPIO_NR(2, 23) +#define GP_I2C_EN_AR1020 IMX_GPIO_NR(7, 13) + +static iomux_v3_cfg_t const i2c_mux_pads[] = { + NEW_PAD_CTRL(MX6_PAD_EIM_A22__GPIO_2_16, WEAK_PULLDOWN), /* mipi I2C enable */ + NEW_PAD_CTRL(MX6_PAD_EIM_A17__GPIO_2_21, WEAK_PULLDOWN), /* LVDS0 I2C enable */ + NEW_PAD_CTRL(MX6_PAD_EIM_A16__GPIO_2_22, WEAK_PULLDOWN), /* LVDS1 I2C enable */ + NEW_PAD_CTRL(MX6_PAD_EIM_CS0__GPIO_2_23, WEAK_PULLDOWN), /* RTC I2C enable */ + NEW_PAD_CTRL(MX6_PAD_GPIO_18__GPIO_7_13, WEAK_PULLDOWN), /* AR1020 I2C enable */ +}; + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + imx_iomux_v3_setup_multiple_pads(i2c_mux_pads, + ARRAY_SIZE(i2c_mux_pads)); + gpio_direction_output(GP_I2C_EN_MIPI, 0); + gpio_direction_output(GP_I2C_EN_LVDS0, 0); + gpio_direction_output(GP_I2C_EN_LVDS1, 0); + gpio_direction_output(GP_I2C_EN_RTC, 0); + gpio_direction_output(GP_I2C_EN_AR1020, 0); + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: Boundary H\n"); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/board/boundary/h/hquad2g.cfg b/board/boundary/h/hquad2g.cfg new file mode 100644 index 00000000000..4c2fd37716e --- /dev/null +++ b/board/boundary/h/hquad2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "../nitrogen6x/ddr-setup.cfg" +#include "../nitrogen6x/1066mhz_4x256mx16.cfg" +#include "../nitrogen6x/clocks.cfg" diff --git a/board/boundary/h/hsolo1g.cfg b/board/boundary/h/hsolo1g.cfg new file mode 100644 index 00000000000..afc42c779fc --- /dev/null +++ b/board/boundary/h/hsolo1g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "../nitrogen6x/ddr-setup.cfg" +#include "../nitrogen6x/800mhz_2x256mx16.cfg" +#include "../nitrogen6x/clocks.cfg" -- cgit v1.2.3