From c043d8d8ce8bf1c1946c87a89b6639db3ebb4243 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 11 Apr 2016 16:41:33 +0800 Subject: board: sama5d2_xplained: change SDHCI GCK's clock source to UPLL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the clock source of the SDHCI's generated clock from PLLA to UPLL clock to align to Linux driver. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann --- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/atmel') diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 04422ce9be..93df7ba32a 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -175,7 +175,7 @@ static void board_sdhci0_hw_init(void) at91_periph_clk_enable(ATMEL_ID_SDMMC0); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); } static void board_sdhci1_hw_init(void) @@ -191,7 +191,7 @@ static void board_sdhci1_hw_init(void) at91_periph_clk_enable(ATMEL_ID_SDMMC1); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); } int board_mmc_init(bd_t *bis) -- cgit v1.2.3