From 2cea8d74dc3a80bbc06aff6b6dcaceb806d563b4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 19 Sep 2018 13:01:55 +0200 Subject: imx: mx7: fix potential overflow in imx_ddr_size() The imx_ddr_size() function may overflow as it is possible to kind of over provision the DDR controller. Fix this by capping it to 2 GB which is the maximum allowed size as per reference manual. Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/mx7/ddr.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index f19aeb8042..9713835bf2 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -196,5 +196,9 @@ unsigned int imx_ddr_size(void) if (field_val <= 29) bits++; + /* cap to max 2 GB */ + if (bits > 31) + bits = 31; + return 1 << bits; } -- cgit v1.2.3 From 2f90c62c8ac09504ee2d94445bd425f35f6a60f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?= Date: Thu, 6 Sep 2018 09:51:53 +0200 Subject: ARM: opos6ul: make the board boot again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 9faa43c4b5e5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl") removes the u-boot,dm-spl properties from the imx6ul.dtsi file and breaks the OPOS6UL board. Add the u-boot,dm-spl properties into *-u-boot.dts files to make the board boot again. Fixes: commit 9faa43c4b5e5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl") Signed-off-by: Sébastien Szymanski Reviewed-by: Tom Rini Reviewed-by: Stefano Babic --- arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/dts/imx6ul-opos6ul.dtsi | 2 -- arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi | 24 ++++++++++++++++++++++++ arch/arm/dts/imx6ul-opos6uldev.dts | 2 -- 4 files changed, 52 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi (limited to 'arch') diff --git a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi new file mode 100644 index 0000000000..4918de388e --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the OPOS6UL SoM + * + * Copyright (C) 2018 Armadeus Systems + */ + +/ { + soc { + u-boot,dm-spl; + }; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6ul-opos6ul.dtsi b/arch/arm/dts/imx6ul-opos6ul.dtsi index d51ad4de20..8f16a0a81c 100644 --- a/arch/arm/dts/imx6ul-opos6ul.dtsi +++ b/arch/arm/dts/imx6ul-opos6ul.dtsi @@ -99,7 +99,6 @@ /* eMMC */ &usdhc1 { - u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; bus-width = <8>; @@ -162,7 +161,6 @@ }; pinctrl_usdhc1: usdhc1grp { - u-boot,dm-spl; fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 diff --git a/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi new file mode 100644 index 0000000000..da8b0392ef --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the OPOS6ULDev board + * + * Copyright (C) 2018 Armadeus Systems + */ + +#include "imx6ul-opos6ul-u-boot.dtsi" + +&aips1 { + u-boot,dm-spl; + + spba-bus@02000000 { + u-boot,dm-spl; + }; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6ul-opos6uldev.dts b/arch/arm/dts/imx6ul-opos6uldev.dts index 9a51d1e54f..0e59ee57fd 100644 --- a/arch/arm/dts/imx6ul-opos6uldev.dts +++ b/arch/arm/dts/imx6ul-opos6uldev.dts @@ -228,7 +228,6 @@ }; &uart1 { - u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; @@ -374,7 +373,6 @@ }; pinctrl_uart1: uart1grp { - u-boot,dm-spl; fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 -- cgit v1.2.3 From 0b6b8a3a199ee74e7da0fb8477ac33e7a65f0cb5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 4 Oct 2018 21:16:42 +0200 Subject: arm: imx: mx5: Make videoskip available on MX5 The board_video_skip() implementation in imx-common/video.c works on i.MX5x as well, so loosen the SoC filter in Makefile to make it available. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/mach-imx/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 733c308670..9b00074483 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -31,10 +31,12 @@ obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o endif +ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o +endif ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o obj-$(CONFIG_FEC_MXC) += mac.o -obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o -- cgit v1.2.3 From ed85f771902b624891062d3c0fbd6fbf2f4d0982 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 10 Oct 2018 10:40:02 +0200 Subject: arm: mx5: Add LDB clock config code Add code to configure PLL4, from which the LDB clock are directly derived. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/include/asm/arch-mx5/clock.h | 1 + arch/arm/mach-imx/mx5/clock.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 0ecbdeede5..6f5ca5888a 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -38,6 +38,7 @@ enum mxc_clock { MXC_NFC_CLK, MXC_PERIPH_CLK, MXC_I2C_CLK, + MXC_LDB_CLK, }; u32 imx_get_uartclk(void); diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 427cb12415..2fabdd2eae 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -838,6 +838,31 @@ static int config_ddr_clk(u32 emi_clk) return 0; } +#ifdef CONFIG_MX53 +static int config_ldb_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + + return config_pll_clk(PLL4_CLOCK, &pll_param); +} +#else +static int config_ldb_clk(u32 ref, u32 freq) +{ + /* Platform not supported */ + return -EINVAL; +} +#endif + /* * This function assumes the expected core clock has to be changed by * modifying the PLL. This is NOT true always but for most of the times, @@ -879,6 +904,10 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) if (config_nfc_clk(freq)) return -EINVAL; break; + case MXC_LDB_CLK: + if (config_ldb_clk(ref, freq)) + return -EINVAL; + break; default: printf("Warning:Unsupported or invalid clock type\n"); } -- cgit v1.2.3 From 39cb4f3c25a1cafbe867d0951d2d54b475a68990 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 4 Oct 2018 21:24:14 +0200 Subject: arm: mx5: Add M53Menlo board Add Menlosystems M53 board, based on the M53 SoM. This board has Ethernet, USB host, USB gadget, UART and LCD on it. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/mach-imx/mx5/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 051b15dbff..29051c40f3 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -30,6 +30,11 @@ config TARGET_KP_IMX53 select MX53 imply CMD_DM +config TARGET_M53MENLO + bool "Support m53menlo" + select MX53 + select SUPPORT_SPL + config TARGET_MX51EVK bool "Support mx51evk" select BOARD_LATE_INIT @@ -89,6 +94,7 @@ source "board/freescale/mx53smd/Kconfig" source "board/ge/mx53ppd/Kconfig" source "board/inversepath/usbarmory/Kconfig" source "board/k+p/kp_imx53/Kconfig" +source "board/menlo/m53menlo/Kconfig" source "board/technologic/ts4800/Kconfig" endif -- cgit v1.2.3 From bf494d7e9b4ad73325b2aef2dc7b90b05dd90264 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:07 +0200 Subject: imx8: add scfw macro definition Add SCFW macro definition. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 ++++++++++++++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 58 ++++++ arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 30 +++ arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 57 ++++++ arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 44 +++++ arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 69 +++++++ arch/arm/include/asm/arch-imx8/sci/types.h | 220 ++++++++++++++++++++++ 7 files changed, 636 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h new file mode 100644 index 0000000000..746c2fa24d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * + */ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Note: Check SCFW API Released DOC before you want to modify something */ +#define SC_RPC_VERSION 1U + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER(MSG) ((MSG)->version) +#define RPC_SIZE(MSG) ((MSG)->size) +#define RPC_SVC(MSG) ((MSG)->svc) +#define RPC_FUNC(MSG) ((MSG)->func) +#define RPC_R8(MSG) ((MSG)->func) +#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) +#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) + +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_ABORT 9U + +/* Types */ + +struct sc_rpc_msg_s { + u8 version; + u8 size; + u8 svc; + u8 func; + union { + s32 i32[(SC_RPC_MAX_MSG - 1U)]; + s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U]; + s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U]; + u32 u32[(SC_RPC_MAX_MSG - 1U)]; + u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U]; + u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U]; + } DATA; +}; + +/* PM RPC */ +#define PM_FUNC_UNKNOWN 0 +#define PM_FUNC_SET_SYS_POWER_MODE 19U +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U +#define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U +#define PM_FUNC_REQ_LOW_POWER_MODE 16U +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U +#define PM_FUNC_SET_CPU_RESUME 21U +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U +#define PM_FUNC_SET_CLOCK_RATE 5U +#define PM_FUNC_GET_CLOCK_RATE 6U +#define PM_FUNC_CLOCK_ENABLE 7U +#define PM_FUNC_SET_CLOCK_PARENT 14U +#define PM_FUNC_GET_CLOCK_PARENT 15U +#define PM_FUNC_RESET 13U +#define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_BOOT 8U +#define PM_FUNC_REBOOT 9U +#define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_CPU_START 11U + +/* MISC RPC */ +#define MISC_FUNC_UNKNOWN 0 +#define MISC_FUNC_SET_CONTROL 1U +#define MISC_FUNC_GET_CONTROL 2U +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U +#define MISC_FUNC_SET_DMA_GROUP 5U +#define MISC_FUNC_SECO_IMAGE_LOAD 8U +#define MISC_FUNC_SECO_AUTHENTICATE 9U +#define MISC_FUNC_SECO_FUSE_WRITE 20U +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U +#define MISC_FUNC_SECO_BUILD_INFO 24U +#define MISC_FUNC_DEBUG_OUT 10U +#define MISC_FUNC_WAVEFORM_CAPTURE 6U +#define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_UNIQUE_ID 19U +#define MISC_FUNC_SET_ARI 3U +#define MISC_FUNC_BOOT_STATUS 7U +#define MISC_FUNC_BOOT_DONE 14U +#define MISC_FUNC_OTP_FUSE_READ 11U +#define MISC_FUNC_OTP_FUSE_WRITE 17U +#define MISC_FUNC_SET_TEMP 12U +#define MISC_FUNC_GET_TEMP 13U +#define MISC_FUNC_GET_BOOT_DEV 16U +#define MISC_FUNC_GET_BUTTON_STATUS 18U + +/* PAD RPC */ +#define PAD_FUNC_UNKNOWN 0 +#define PAD_FUNC_SET_MUX 1U +#define PAD_FUNC_GET_MUX 6U +#define PAD_FUNC_SET_GP 2U +#define PAD_FUNC_GET_GP 7U +#define PAD_FUNC_SET_WAKEUP 4U +#define PAD_FUNC_GET_WAKEUP 9U +#define PAD_FUNC_SET_ALL 5U +#define PAD_FUNC_GET_ALL 10U +#define PAD_FUNC_SET 15U +#define PAD_FUNC_GET 16U +#define PAD_FUNC_SET_GP_28FDSOI 11U +#define PAD_FUNC_GET_GP_28FDSOI 12U +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U + +/* RM RPC */ +#define RM_FUNC_UNKNOWN 0 +#define RM_FUNC_PARTITION_ALLOC 1U +#define RM_FUNC_SET_CONFIDENTIAL 31U +#define RM_FUNC_PARTITION_FREE 2U +#define RM_FUNC_GET_DID 26U +#define RM_FUNC_PARTITION_STATIC 3U +#define RM_FUNC_PARTITION_LOCK 4U +#define RM_FUNC_GET_PARTITION 5U +#define RM_FUNC_SET_PARENT 6U +#define RM_FUNC_MOVE_ALL 7U +#define RM_FUNC_ASSIGN_RESOURCE 8U +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U +#define RM_FUNC_SET_MASTER_SID 11U +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U +#define RM_FUNC_IS_RESOURCE_OWNED 13U +#define RM_FUNC_IS_RESOURCE_MASTER 14U +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U +#define RM_FUNC_GET_RESOURCE_INFO 16U +#define RM_FUNC_MEMREG_ALLOC 17U +#define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FREE 18U +#define RM_FUNC_FIND_MEMREG 30U +#define RM_FUNC_ASSIGN_MEMREG 19U +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U +#define RM_FUNC_IS_MEMREG_OWNED 21U +#define RM_FUNC_GET_MEMREG_INFO 22U +#define RM_FUNC_ASSIGN_PAD 23U +#define RM_FUNC_SET_PAD_MOVABLE 24U +#define RM_FUNC_IS_PAD_OWNED 25U +#define RM_FUNC_DUMP 27U + +#endif /* SC_RPC_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h new file mode 100644 index 0000000000..d0ff5c5c41 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_SCI_H +#define _SC_SCI_H + +#include +#include +#include +#include +#include +#include +#include +#include + +static inline int sc_err_to_linux(sc_err_t err) +{ + int ret; + + switch (err) { + case SC_ERR_NONE: + return 0; + case SC_ERR_VERSION: + case SC_ERR_CONFIG: + case SC_ERR_PARM: + ret = -EINVAL; + break; + case SC_ERR_NOACCESS: + case SC_ERR_LOCKED: + case SC_ERR_UNAVAILABLE: + ret = -EACCES; + break; + case SC_ERR_NOTFOUND: + case SC_ERR_NOPOWER: + ret = -ENODEV; + break; + case SC_ERR_IPC: + ret = -EIO; + break; + case SC_ERR_BUSY: + ret = -EBUSY; + break; + case SC_ERR_FAIL: + ret = -EIO; + break; + default: + ret = 0; + break; + } + + debug("%s %d %d\n", __func__, err, ret); + + return ret; +} + +#endif diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h new file mode 100644 index 0000000000..5d17b553d7 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Defines for sc_misc_boot_status_t */ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ + +/* Defines for sc_misc_temp_t */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ +#define SC_MISC_REL_CONTAINER 2U /* Release container */ + +typedef u8 sc_misc_boot_status_t; + +#endif /* SC_MISC_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h new file mode 100644 index 0000000000..905c56834e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Defines for sc_pad_config_t */ +#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ +#define SC_PAD_CONFIG_OD 1U /* Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ + +/* Defines for sc_pad_iso_t */ +#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ + +/* Defines for sc_pad_28fdsoi_dse_t */ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength dual volt */ + +/* Defines for sc_pad_28fdsoi_ps_t */ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ + +/* Defines for sc_pad_28fdsoi_pus_t */ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ + +/* Defines for sc_pad_wakeup_t */ +#define SC_PAD_WAKEUP_OFF 0U /* Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ + +#endif /* SC_PAD_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h new file mode 100644 index 0000000000..9008b85c6f --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Defines for sc_pm_power_mode_t */ +#define SC_PM_PW_MODE_OFF 0U /* Power off */ +#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ +#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /* Power on */ + +/* Defines for sc_pm_clk_t */ +#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ +#define SC_PM_CLK_PER 2U /* Peripheral clock */ +#define SC_PM_CLK_PHY 3U /* Phy clock */ +#define SC_PM_CLK_MISC 4U /* Misc clock */ +#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /* CPU clock */ +#define SC_PM_CLK_PLL 4U /* PLL */ +#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ + +/* Defines for sc_pm_clk_mode_t */ +#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ + +typedef u8 sc_pm_power_mode_t; +typedef u8 sc_pm_clk_t; +typedef u8 sc_pm_clk_mode_t; +typedef u8 sc_pm_clk_parent_t; +typedef u32 sc_pm_clock_rate_t; + +#endif /* SC_PM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h new file mode 100644 index 0000000000..ed303881e7 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +#include + +/* Defines for type widths */ +#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ + +/* Defines for ALL parameters */ +#define SC_RM_PT_ALL ((sc_rm_pt_t)UINT8_MAX) /* All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */ + +/* Defines for sc_rm_spa_t */ +#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ + +/* Defines for sc_rm_perm_t */ +#define SC_RM_PERM_NONE 0U /* No access */ +#define SC_RM_PERM_SEC_R 1U /* Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /* Full access */ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef u8 sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef u8 sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef u8 sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef u16 sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef u8 sc_rm_spa_t; + +typedef u8 sc_rm_perm_t; + +#endif /* SC_RM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h new file mode 100644 index 0000000000..9eadc88592 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/types.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ +#include + +/* Defines */ +/* + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef u64 sc_ipc_t; + +/* Defines for common frequencies */ +#define SC_32KHZ 32768U /* 32KHz */ +#define SC_10MHZ 10000000U /* 10MHz */ +#define SC_20MHZ 20000000U /* 20MHz */ +#define SC_25MHZ 25000000U /* 25MHz */ +#define SC_27MHZ 27000000U /* 27MHz */ +#define SC_40MHZ 40000000U /* 40MHz */ +#define SC_45MHZ 45000000U /* 45MHz */ +#define SC_50MHZ 50000000U /* 50MHz */ +#define SC_60MHZ 60000000U /* 60MHz */ +#define SC_66MHZ 66666666U /* 66MHz */ +#define SC_74MHZ 74250000U /* 74.25MHz */ +#define SC_80MHZ 80000000U /* 80MHz */ +#define SC_83MHZ 83333333U /* 83MHz */ +#define SC_84MHZ 84375000U /* 84.37MHz */ +#define SC_100MHZ 100000000U /* 100MHz */ +#define SC_125MHZ 125000000U /* 125MHz */ +#define SC_133MHZ 133333333U /* 133MHz */ +#define SC_135MHZ 135000000U /* 135MHz */ +#define SC_150MHZ 150000000U /* 150MHz */ +#define SC_160MHZ 160000000U /* 160MHz */ +#define SC_166MHZ 166666666U /* 166MHz */ +#define SC_175MHZ 175000000U /* 175MHz */ +#define SC_180MHZ 180000000U /* 180MHz */ +#define SC_200MHZ 200000000U /* 200MHz */ +#define SC_250MHZ 250000000U /* 250MHz */ +#define SC_266MHZ 266666666U /* 266MHz */ +#define SC_300MHZ 300000000U /* 300MHz */ +#define SC_312MHZ 312500000U /* 312.5MHZ */ +#define SC_320MHZ 320000000U /* 320MHz */ +#define SC_325MHZ 325000000U /* 325MHz */ +#define SC_333MHZ 333333333U /* 333MHz */ +#define SC_350MHZ 350000000U /* 350MHz */ +#define SC_372MHZ 372000000U /* 372MHz */ +#define SC_375MHZ 375000000U /* 375MHz */ +#define SC_400MHZ 400000000U /* 400MHz */ +#define SC_500MHZ 500000000U /* 500MHz */ +#define SC_594MHZ 594000000U /* 594MHz */ +#define SC_625MHZ 625000000U /* 625MHz */ +#define SC_640MHZ 640000000U /* 640MHz */ +#define SC_650MHZ 650000000U /* 650MHz */ +#define SC_667MHZ 666666667U /* 667MHz */ +#define SC_675MHZ 675000000U /* 675MHz */ +#define SC_700MHZ 700000000U /* 700MHz */ +#define SC_720MHZ 720000000U /* 720MHz */ +#define SC_750MHZ 750000000U /* 750MHz */ +#define SC_800MHZ 800000000U /* 800MHz */ +#define SC_850MHZ 850000000U /* 850MHz */ +#define SC_900MHZ 900000000U /* 900MHz */ +#define SC_1000MHZ 1000000000U /* 1GHz */ +#define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1188MHZ 1188000000U /* 1.188GHz */ +#define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1280MHZ 1280000000U /* 1.28GHz */ +#define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1400MHZ 1400000000U /* 1.4GHz */ +#define SC_1500MHZ 1500000000U /* 1.5GHz */ +#define SC_1600MHZ 1600000000U /* 1.6GHz */ +#define SC_1800MHZ 1800000000U /* 1.8GHz */ +#define SC_2000MHZ 2000000000U /* 2.0GHz */ +#define SC_2112MHZ 2112000000U /* 2.12GHz */ + +/* Defines for 24M related frequencies */ +#define SC_8MHZ 8000000U /* 8MHz */ +#define SC_12MHZ 12000000U /* 12MHz */ +#define SC_19MHZ 19800000U /* 19.8MHz */ +#define SC_24MHZ 24000000U /* 24MHz */ +#define SC_48MHZ 48000000U /* 48MHz */ +#define SC_120MHZ 120000000U /* 120MHz */ +#define SC_132MHZ 132000000U /* 132MHz */ +#define SC_144MHZ 144000000U /* 144MHz */ +#define SC_192MHZ 192000000U /* 192MHz */ +#define SC_211MHZ 211200000U /* 211.2MHz */ +#define SC_240MHZ 240000000U /* 240MHz */ +#define SC_264MHZ 264000000U /* 264MHz */ +#define SC_352MHZ 352000000U /* 352MHz */ +#define SC_360MHZ 360000000U /* 360MHz */ +#define SC_384MHZ 384000000U /* 384MHz */ +#define SC_396MHZ 396000000U /* 396MHz */ +#define SC_432MHZ 432000000U /* 432MHz */ +#define SC_480MHZ 480000000U /* 480MHz */ +#define SC_600MHZ 600000000U /* 600MHz */ +#define SC_744MHZ 744000000U /* 744MHz */ +#define SC_792MHZ 792000000U /* 792MHz */ +#define SC_864MHZ 864000000U /* 864MHz */ +#define SC_960MHZ 960000000U /* 960MHz */ +#define SC_1056MHZ 1056000000U /* 1056MHz */ +#define SC_1104MHZ 1104000000U /* 1104MHz */ +#define SC_1200MHZ 1200000000U /* 1.2GHz */ +#define SC_1464MHZ 1464000000U /* 1.464GHz */ +#define SC_2400MHZ 2400000000U /* 2.4GHz */ + +/* Defines for A/V related frequencies */ +#define SC_62MHZ 62937500U /* 62.9375MHz */ +#define SC_755MHZ 755250000U /* 755.25MHz */ + +/* Defines for type widths */ +#define SC_FADDR_W 36U /* Width of sc_faddr_t */ +#define SC_BOOL_W 1U /* Width of sc_bool_t */ +#define SC_ERR_W 4U /* Width of sc_err_t */ +#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ + +/* Defines for sc_bool_t */ +#define SC_FALSE ((sc_bool_t)0U) +#define SC_TRUE ((sc_bool_t)1U) + +/* Defines for sc_err_t */ +#define SC_ERR_NONE 0U /* Success */ +#define SC_ERR_VERSION 1U /* Incompatible API version */ +#define SC_ERR_CONFIG 2U /* Configuration error */ +#define SC_ERR_PARM 3U /* Bad parameter */ +#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ +#define SC_ERR_LOCKED 5U /* Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /* Not found */ +#define SC_ERR_NOPOWER 8U /* No power */ +#define SC_ERR_IPC 9U /* Generic IPC error */ +#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /* General I/O failure */ +#define SC_ERR_LAST 12U + +/* Defines for sc_ctrl_t. */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_LAST 46U + +#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */ + +/* Types */ + +/* This type is used to store a boolean */ +typedef u8 sc_bool_t; + +/* This type is used to store a system (full-size) address. */ +typedef u64 sc_faddr_t; + +/* This type is used to indicate error response for most functions. */ +typedef u8 sc_err_t; + +/* + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +typedef u16 sc_rsrc_t; + +/* This type is used to indicate a control. */ +typedef u8 sc_ctrl_t; + +/* + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef u16 sc_pad_t; + +#endif /* SC_TYPES_H */ -- cgit v1.2.3 From b2b8b9be2fda11192b2c50e1edf2b9e652471bc2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:08 +0200 Subject: imx: add Kconfig entry for i.MX8QXP Add Kconfig entry for i.MX8QXP Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/Kconfig | 8 ++++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 13 +++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Kconfig (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ccf2a844be..4f597b7ce6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -668,6 +668,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_IMX8 + bool "NXP i.MX8 platform" + select ARM64 + select DM + select OF_CONTROL + config ARCH_MX8M bool "NXP i.MX8M platform" select ARM64 @@ -1407,6 +1413,8 @@ source "arch/arm/mach-imx/mx7/Kconfig" source "arch/arm/mach-imx/mx7ulp/Kconfig" +source "arch/arm/mach-imx/imx8/Kconfig" + source "arch/arm/mach-imx/mx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 9b00074483..d6dcbe0c7c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -143,3 +143,4 @@ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_ARCH_IMX8) += imx8/ diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig new file mode 100644 index 0000000000..28910c1509 --- /dev/null +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -0,0 +1,13 @@ +if ARCH_IMX8 + +config IMX8 + bool + +config IMX8QXP + select IMX8 + bool + +config SYS_SOC + default "imx8" + +endif -- cgit v1.2.3 From a6bba0bd00e2cdf8010615e9ddf77ab978857c85 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:09 +0200 Subject: arm: build mach-imx for i.MX8 Build mach-imx for i.MX8 Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8f50560434..7285913b41 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -105,7 +105,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif -- cgit v1.2.3 From 60b9de4f708ce1eae1eeb362e9b9ea32a63e4ebd Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:10 +0200 Subject: arm: global_data: add scu_dev for i.MX8 Add scu_dev for i.MX8, this will be used as a handle to communite with SCU from A35. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/global_data.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 287a7bd5b1..c3ee5f0c7b 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -74,6 +74,10 @@ struct arch_global_data { #if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) unsigned long mem2_clk; #endif + +#ifdef CONFIG_ARCH_IMX8 + struct udevice *scu_dev; +#endif }; #include -- cgit v1.2.3 From ad9d40acb4e67d708264b5caec6e281a28d14344 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:12 +0200 Subject: misc: imx8: add scfw api impementation Add clk/misc/pad/pm/rm scfw api implementaion for different drivers to invoke. The low level code is using misc_call to invoke imx8_scu driver. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/sci/sci.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index d0ff5c5c41..d1621669e2 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -55,4 +55,34 @@ static inline int sc_err_to_linux(sc_err_t err) return ret; } +/* PM API*/ +int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); +int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable, sc_bool_t autog); + +/* MISC API */ +int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, + u32 *val); +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); +void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); +int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); + +/* RM API */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); +int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end); +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); + +/* PAD API */ +int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); #endif -- cgit v1.2.3 From 707effeafdeb77be31a3e7a135dea14903066a55 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:13 +0200 Subject: imx: boot_mode: Add FLEXSPI boot entry i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/mach-imx/boot_mode.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h index 8766e9d180..3a483b6afa 100644 --- a/arch/arm/include/asm/mach-imx/boot_mode.h +++ b/arch/arm/include/asm/mach-imx/boot_mode.h @@ -25,6 +25,7 @@ enum boot_device { MMC4_BOOT, NAND_BOOT, QSPI_BOOT, + FLEXSPI_BOOT, USB_BOOT, UNKNOWN_BOOT, BOOT_DEV_NUM = UNKNOWN_BOOT, -- cgit v1.2.3 From 8c518722480aca0275107ab13f68fffc2688afd4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:14 +0200 Subject: imx8: add imx-regs header file Add imx-regs header file to include the register base definition Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/imx-regs.h | 46 +++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h new file mode 100644 index 0000000000..af0fb5154b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_REGS_H__ +#define __ASM_ARCH_IMX8_REGS_H__ + +#define LPUART_BASE 0x5A060000 + +#define GPT1_BASE_ADDR 0x5D140000 +#define SCU_LPUART_BASE 0x33220000 +#define GPIO1_BASE_ADDR 0x5D080000 +#define GPIO2_BASE_ADDR 0x5D090000 +#define GPIO3_BASE_ADDR 0x5D0A0000 +#define GPIO4_BASE_ADDR 0x5D0B0000 +#define GPIO5_BASE_ADDR 0x5D0C0000 +#define GPIO6_BASE_ADDR 0x5D0D0000 +#define GPIO7_BASE_ADDR 0x5D0E0000 +#define GPIO8_BASE_ADDR 0x5D0F0000 +#define LPI2C1_BASE_ADDR 0x5A800000 +#define LPI2C2_BASE_ADDR 0x5A810000 +#define LPI2C3_BASE_ADDR 0x5A820000 +#define LPI2C4_BASE_ADDR 0x5A830000 +#define LPI2C5_BASE_ADDR 0x5A840000 + +#ifdef CONFIG_IMX8QXP +#define LVDS0_PHYCTRL_BASE 0x56221000 +#define LVDS1_PHYCTRL_BASE 0x56241000 +#define MIPI0_SS_BASE 0x56220000 +#define MIPI1_SS_BASE 0x56240000 +#endif + +#define APBH_DMA_ARB_BASE_ADDR 0x5B810000 +#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +#define PASS_OVER_INFO_ADDR 0x0010fe00 + +#define USB_BASE_ADDR 0x5b0d0000 +#define USB_PHY0_BASE_ADDR 0x5b100000 + +#endif /* __ASM_ARCH_IMX8_REGS_H__ */ -- cgit v1.2.3 From 0468be6e7c51296e8f3dcc4ba0bad84a204cc91a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:15 +0200 Subject: imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined Include i.MX8QXP pin header when CONFIG_IMX8QXP defined, if no SoC macro defined, report error. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h new file mode 100644 index 0000000000..dcced1010b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_PINS_H__ +#define __ASM_ARCH_IMX8_PINS_H__ + +#if defined(CONFIG_IMX8QXP) +#include +#else +#error "No pin header" +#endif + +#endif /* __ASM_ARCH_IMX8_PINS_H__ */ -- cgit v1.2.3 From 5710a48afc0fbc5a90727404f1da1df52af99c46 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:16 +0200 Subject: imx: add i.MX8 cpu type Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/include/asm/arch-imx/cpu.h | 5 +++++ arch/arm/include/asm/mach-imx/sys_proto.h | 3 +++ 2 files changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 62df1b9ad2..cf6303c3f5 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,12 +25,14 @@ #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 #define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 #define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_0 0x10 @@ -41,6 +43,9 @@ #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 + #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 #define BOARD_VER_OFFSET 0x8 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index d1d6cbc462..f8890b57da 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -27,6 +27,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8() (is_soc_type(MXC_SOC_IMX8)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) @@ -41,6 +42,8 @@ #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) + #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) -- cgit v1.2.3 From fa64d8429b525f7db2e22ed67d1d3c682e89078c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:17 +0200 Subject: armv8: add cpu core helper functions Add helper functions to identify different armv8 variants. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/armv8/cpu.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 arch/arm/include/asm/armv8/cpu.h (limited to 'arch') diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h new file mode 100644 index 0000000000..40d54dc85a --- /dev/null +++ b/arch/arm/include/asm/armv8/cpu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << 0x4) + +static inline unsigned int read_midr(void) +{ + unsigned long val; + + asm volatile("mrs %0, midr_el1" : "=r" (val)); + + return val; +} + +#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) +#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) +#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) -- cgit v1.2.3 From 60d33fcd1976e6a25c070c62d6f1064020d686bd Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:18 +0200 Subject: imx8: add basic cpu support Add basic cpu support, including cpu revision, cpu type, cpu core detection. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/mach-imx/imx8/Makefile | 7 ++++ arch/arm/mach-imx/imx8/cpu.c | 93 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/cpu.c (limited to 'arch') diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile new file mode 100644 index 0000000000..57876139a1 --- /dev/null +++ b/arch/arm/mach-imx/imx8/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c new file mode 100644 index 0000000000..0b841e291d --- /dev/null +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_cpu_rev(void) +{ + u32 id = 0, rev = 0; + int ret; + + ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id); + if (ret) + return 0; + + rev = (id >> 5) & 0xf; + id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ + + return (id << 12) | rev; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +const char *get_imx8_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX8QXP: + return "8QXP"; + default: + return "??"; + } +} + +const char *get_imx8_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_A: + return "A"; + case CHIP_REV_B: + return "B"; + default: + return "?"; + } +} + +const char *get_core_name(void) +{ + if (is_cortex_a35()) + return "A35"; + else + return "?"; +} + +int print_cpuinfo(void) +{ + struct udevice *dev; + struct clk cpu_clk; + int ret; + + ret = uclass_get_device(UCLASS_CPU, 0, &dev); + if (ret) + return 0; + + ret = clk_get_by_index(dev, 0, &cpu_clk); + if (ret) { + dev_err(dev, "failed to clk\n"); + return 0; + } + + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n", + get_imx8_type((cpurev & 0xFF000) >> 12), + get_imx8_rev((cpurev & 0xFFF)), + get_core_name(), + clk_get_rate(&cpu_clk) / 1000000); + + return 0; +} +#endif -- cgit v1.2.3 From 8aa1505b59159cf8f52ba7441dd9e71c3caf1ded Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:19 +0200 Subject: imx8: add boot device detection Add get_boot_device to detect boot device. Add print_bootinfo to print the boot device info. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/sys_proto.h | 10 ++++ arch/arm/mach-imx/imx8/cpu.c | 85 ++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h new file mode 100644 index 0000000000..f9a3016132 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#include +#include + +enum boot_device get_boot_device(void); +int print_bootinfo(void); diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 0b841e291d..90b6ea4211 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -11,8 +11,10 @@ #include #include #include +#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -91,3 +93,86 @@ int print_cpuinfo(void) return 0; } #endif + +int print_bootinfo(void) +{ + enum boot_device bt_dev = get_boot_device(); + + puts("Boot: "); + switch (bt_dev) { + case SD1_BOOT: + puts("SD0\n"); + break; + case SD2_BOOT: + puts("SD1\n"); + break; + case SD3_BOOT: + puts("SD2\n"); + break; + case MMC1_BOOT: + puts("MMC0\n"); + break; + case MMC2_BOOT: + puts("MMC1\n"); + break; + case MMC3_BOOT: + puts("MMC2\n"); + break; + case FLEXSPI_BOOT: + puts("FLEXSPI\n"); + break; + case SATA_BOOT: + puts("SATA\n"); + break; + case NAND_BOOT: + puts("NAND\n"); + break; + case USB_BOOT: + puts("USB\n"); + break; + default: + printf("Unknown device %u\n", bt_dev); + break; + } + + return 0; +} + +enum boot_device get_boot_device(void) +{ + enum boot_device boot_dev = SD1_BOOT; + + sc_rsrc_t dev_rsrc; + + sc_misc_get_boot_dev(-1, &dev_rsrc); + + switch (dev_rsrc) { + case SC_R_SDHC_0: + boot_dev = MMC1_BOOT; + break; + case SC_R_SDHC_1: + boot_dev = SD2_BOOT; + break; + case SC_R_SDHC_2: + boot_dev = SD3_BOOT; + break; + case SC_R_NAND: + boot_dev = NAND_BOOT; + break; + case SC_R_FSPI_0: + boot_dev = FLEXSPI_BOOT; + break; + case SC_R_SATA_0: + boot_dev = SATA_BOOT; + break; + case SC_R_USB_0: + case SC_R_USB_1: + case SC_R_USB_2: + boot_dev = USB_BOOT; + break; + default: + break; + } + + return boot_dev; +} -- cgit v1.2.3 From c1aae21d89108adcfc4316a5a073e3ff1f972a2c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:20 +0200 Subject: imx8: implement mmc_get_env_dev Implement mmc_get_env_dev for i.MX8. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/mach-imx/imx8/cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 90b6ea4211..0cacaa895c 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -176,3 +176,35 @@ enum boot_device get_boot_device(void) return boot_dev; } + +#ifdef CONFIG_ENV_IS_IN_MMC +__weak int board_mmc_get_env_dev(int devno) +{ + return CONFIG_SYS_MMC_ENV_DEV; +} + +int mmc_get_env_dev(void) +{ + sc_rsrc_t dev_rsrc; + int devno; + + sc_misc_get_boot_dev(-1, &dev_rsrc); + + switch (dev_rsrc) { + case SC_R_SDHC_0: + devno = 0; + break; + case SC_R_SDHC_1: + devno = 1; + break; + case SC_R_SDHC_2: + devno = 2; + break; + default: + /* If not boot from sd/mmc, use default value */ + return CONFIG_SYS_MMC_ENV_DEV; + } + + return board_mmc_get_env_dev(devno); +} +#endif -- cgit v1.2.3 From 930b59529176bb05ea61ef9a40bf6384227f991e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:21 +0200 Subject: imx8: add mmu and dram related functions Add mmu memmap, some memory regions are reserved by M4, Arm Trusted Firmware, so need to get memreg using SCFW API and setup the memmap. Add dram_init, dram_init_banksize, get_effective_memsize functions, according to the memreg. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/mach-imx/imx8/cpu.c | 284 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 284 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 0cacaa895c..f73ce2fde3 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -208,3 +209,286 @@ int mmc_get_env_dev(void) return board_mmc_get_env_dev(devno); } #endif + +#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */ + +static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end) +{ + sc_faddr_t start, end; + int ret; + bool owned; + + owned = sc_rm_is_memreg_owned(-1, mr); + if (owned) { + ret = sc_rm_get_memreg_info(-1, mr, &start, &end); + if (ret) { + printf("Memreg get info failed, %d\n", ret); + return -EINVAL; + } + debug("0x%llx -- 0x%llx\n", start, end); + *addr_start = start; + *addr_end = end; + + return 0; + } + + return -EINVAL; +} + +phys_size_t get_effective_memsize(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end, end1; + int err; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + + for (mr = 0; mr < 64; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + /* Too small memory region, not use it */ + if (start > end) + continue; + + /* Find the memory region runs the u-boot */ + if (start >= PHYS_SDRAM_1 && start <= end1 && + (start <= CONFIG_SYS_TEXT_BASE && + end >= CONFIG_SYS_TEXT_BASE)) { + if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + + PHYS_SDRAM_1_SIZE)) + return (end - PHYS_SDRAM_1 + 1); + else + return PHYS_SDRAM_1_SIZE; + } + } + } + + return PHYS_SDRAM_1_SIZE; +} + +int dram_init(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end, end1, end2; + int err; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + for (mr = 0; mr < 64; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + /* Too small memory region, not use it */ + if (start > end) + continue; + + if (start >= PHYS_SDRAM_1 && start <= end1) { + if ((end + 1) <= end1) + gd->ram_size += end - start + 1; + else + gd->ram_size += end1 - start; + } else if (start >= PHYS_SDRAM_2 && start <= end2) { + if ((end + 1) <= end2) + gd->ram_size += end - start + 1; + else + gd->ram_size += end2 - start; + } + } + } + + /* If error, set to the default value */ + if (!gd->ram_size) { + gd->ram_size = PHYS_SDRAM_1_SIZE; + gd->ram_size += PHYS_SDRAM_2_SIZE; + } + return 0; +} + +static void dram_bank_sort(int current_bank) +{ + phys_addr_t start; + phys_size_t size; + + while (current_bank > 0) { + if (gd->bd->bi_dram[current_bank - 1].start > + gd->bd->bi_dram[current_bank].start) { + start = gd->bd->bi_dram[current_bank - 1].start; + size = gd->bd->bi_dram[current_bank - 1].size; + + gd->bd->bi_dram[current_bank - 1].start = + gd->bd->bi_dram[current_bank].start; + gd->bd->bi_dram[current_bank - 1].size = + gd->bd->bi_dram[current_bank].size; + + gd->bd->bi_dram[current_bank].start = start; + gd->bd->bi_dram[current_bank].size = size; + } + current_bank--; + } +} + +int dram_init_banksize(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end, end1, end2; + int i = 0; + int err; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + + for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + start = roundup(start, MEMSTART_ALIGNMENT); + if (start > end) /* Small memory region, no use it */ + continue; + + if (start >= PHYS_SDRAM_1 && start <= end1) { + gd->bd->bi_dram[i].start = start; + + if ((end + 1) <= end1) + gd->bd->bi_dram[i].size = + end - start + 1; + else + gd->bd->bi_dram[i].size = end1 - start; + + dram_bank_sort(i); + i++; + } else if (start >= PHYS_SDRAM_2 && start <= end2) { + gd->bd->bi_dram[i].start = start; + + if ((end + 1) <= end2) + gd->bd->bi_dram[i].size = + end - start + 1; + else + gd->bd->bi_dram[i].size = end2 - start; + + dram_bank_sort(i); + i++; + } + } + } + + /* If error, set to the default value */ + if (!i) { + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + } + + return 0; +} + +static u64 get_block_attrs(sc_faddr_t addr_start) +{ + u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + if ((addr_start >= PHYS_SDRAM_1 && + addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) || + (addr_start >= PHYS_SDRAM_2 && + addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) + return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); + + return attr; +} + +static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_faddr_t end1, end2; + + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; + end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + + if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) { + if ((addr_end + 1) > end1) + return end1 - addr_start; + } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) { + if ((addr_end + 1) > end2) + return end2 - addr_start; + } + + return (addr_end - addr_start + 1); +} + +#define MAX_PTE_ENTRIES 512 +#define MAX_MEM_MAP_REGIONS 16 + +static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS]; +struct mm_region *mem_map = imx8_mem_map; + +void enable_caches(void) +{ + sc_rm_mr_t mr; + sc_faddr_t start, end; + int err, i; + + /* Create map for registers access from 0x1c000000 to 0x80000000*/ + imx8_mem_map[0].virt = 0x1c000000UL; + imx8_mem_map[0].phys = 0x1c000000UL; + imx8_mem_map[0].size = 0x64000000UL; + imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + i = 1; + for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) { + err = get_owned_memreg(mr, &start, &end); + if (!err) { + imx8_mem_map[i].virt = start; + imx8_mem_map[i].phys = start; + imx8_mem_map[i].size = get_block_size(start, end); + imx8_mem_map[i].attrs = get_block_attrs(start); + i++; + } + } + + if (i < MAX_MEM_MAP_REGIONS) { + imx8_mem_map[i].size = 0; + imx8_mem_map[i].attrs = 0; + } else { + puts("Error, need more MEM MAP REGIONS reserved\n"); + icache_enable(); + return; + } + + for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) { + debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n", + i, imx8_mem_map[i].virt, imx8_mem_map[i].phys, + imx8_mem_map[i].size, imx8_mem_map[i].attrs); + } + + icache_enable(); + dcache_enable(); +} + +#ifndef CONFIG_SYS_DCACHE_OFF +u64 get_page_table_size(void) +{ + u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); + u64 size = 0; + + /* + * For each memory region, the max table size: + * 2 level 3 tables + 2 level 2 tables + 1 level 1 table + */ + size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt; + + /* + * We need to duplicate our page table once to have an emergency pt to + * resort to when splitting page tables later on + */ + size *= 2; + + /* + * We may need to split page tables later on if dcache settings change, + * so reserve up to 4 (random pick) page tables for that. + */ + size += one_pt * 4; + + return size; +} +#endif -- cgit v1.2.3 From 1ef20a3d812281b5979ec0cb030b91124987e0b6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:22 +0200 Subject: imx8: add arch_cpu_init arch_cpu_init_dm Add arch_cpu_init(_dm) mainly to open the channel between ACore and SCU. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/sys_proto.h | 9 +++++ arch/arm/mach-imx/imx8/cpu.c | 53 +++++++++++++++++++++++++++++- 2 files changed, 61 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index f9a3016132..73ffaba7d5 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -6,5 +6,14 @@ #include #include +struct pass_over_info_t { + u16 barker; + u16 len; + u32 g_bt_cfg_shadow; + u32 card_address_mode; + u32 bad_block_count_met; + u32 g_ap_mu; +}; + enum boot_device get_boot_device(void); int print_bootinfo(void); diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f73ce2fde3..d80b4b175d 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -95,6 +95,57 @@ int print_cpuinfo(void) } #endif +#define BT_PASSOVER_TAG 0x504F +struct pass_over_info_t *get_pass_over_info(void) +{ + struct pass_over_info_t *p = + (struct pass_over_info_t *)PASS_OVER_INFO_ADDR; + + if (p->barker != BT_PASSOVER_TAG || + p->len != sizeof(struct pass_over_info_t)) + return NULL; + + return p; +} + +int arch_cpu_init(void) +{ + struct pass_over_info_t *pass_over = get_pass_over_info(); + + if (pass_over && pass_over->g_ap_mu == 0) { + /* + * When ap_mu is 0, means the U-Boot booted + * from first container + */ + sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS); + } + + return 0; +} + +int arch_cpu_init_dm(void) +{ + struct udevice *devp; + int node, ret; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); + ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu", + offset_to_ofnode(node), &devp); + + if (ret) { + printf("could not find scu %d\n", ret); + return ret; + } + + ret = device_probe(devp); + if (ret) { + printf("scu probe failed %d\n", ret); + return ret; + } + + return 0; +} + int print_bootinfo(void) { enum boot_device bt_dev = get_boot_device(); @@ -252,7 +303,7 @@ phys_size_t get_effective_memsize(void) if (start > end) continue; - /* Find the memory region runs the u-boot */ + /* Find the memory region runs the U-Boot */ if (start >= PHYS_SDRAM_1 && start <= end1 && (start <= CONFIG_SYS_TEXT_BASE && end >= CONFIG_SYS_TEXT_BASE)) { -- cgit v1.2.3 From 70b4b49b91e2bfb148307dc4e35594740ba00514 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 18 Oct 2018 14:28:23 +0200 Subject: imx8: cpu: add function for reading FEC MAC from fuse FEC driver requires imx_get_mac_from_fuse(). Add it in preparation for ENETx support. Signed-off-by: Anatolij Gustschin Cc: Stefano Babic Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index d80b4b175d..da34a94a23 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -543,3 +543,41 @@ u64 get_page_table_size(void) return size; } #endif + +#define FUSE_MAC0_WORD0 708 +#define FUSE_MAC0_WORD1 709 +#define FUSE_MAC1_WORD0 710 +#define FUSE_MAC1_WORD1 711 + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + u32 word[2], val[2] = {}; + int i, ret; + + if (dev_id == 0) { + word[0] = FUSE_MAC0_WORD0; + word[1] = FUSE_MAC0_WORD1; + } else { + word[0] = FUSE_MAC1_WORD0; + word[1] = FUSE_MAC1_WORD1; + } + + for (i = 0; i < 2; i++) { + ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]); + if (ret < 0) + goto err; + } + + mac[0] = val[0]; + mac[1] = val[0] >> 8; + mac[2] = val[0] >> 16; + mac[3] = val[0] >> 24; + mac[4] = val[1]; + mac[5] = val[1] >> 8; + + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +err: + printf("%s: fuse %d, err: %d\n", __func__, word[i], ret); +} -- cgit v1.2.3 From 2fdb1a1df925f885afc677e61755125844a9b7ef Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 18 Oct 2018 14:28:24 +0200 Subject: imx8: cpu: add uclass based CPU driver print_cpuinfo() in board init code requires uclass CPU driver, add it to be able to display CPU info when CONFIG_DISPLAY_CPUINFO option is enabled. CPU node in DT will have to include 'clocks' and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo() to work as expected. The driver outputs info for i.MX8QXP Rev A and Rev B CPUs. Signed-off-by: Anatolij Gustschin Cc: Stefano Babic Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 5 +- arch/arm/mach-imx/imx8/cpu.c | 215 +++++++++++++++++++++++------------- 2 files changed, 142 insertions(+), 78 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index cf6303c3f5..2af79659d2 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,6 +25,7 @@ #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 #define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ @@ -43,8 +44,8 @@ #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 -#define CHIP_REV_A 0x0 -#define CHIP_REV_B 0x1 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index da34a94a23..f093f34ca5 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -19,82 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_cpu_rev(void) -{ - u32 id = 0, rev = 0; - int ret; - - ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id); - if (ret) - return 0; - - rev = (id >> 5) & 0xf; - id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ - - return (id << 12) | rev; -} - -#ifdef CONFIG_DISPLAY_CPUINFO -const char *get_imx8_type(u32 imxtype) -{ - switch (imxtype) { - case MXC_CPU_IMX8QXP: - return "8QXP"; - default: - return "??"; - } -} - -const char *get_imx8_rev(u32 rev) -{ - switch (rev) { - case CHIP_REV_A: - return "A"; - case CHIP_REV_B: - return "B"; - default: - return "?"; - } -} - -const char *get_core_name(void) -{ - if (is_cortex_a35()) - return "A35"; - else - return "?"; -} - -int print_cpuinfo(void) -{ - struct udevice *dev; - struct clk cpu_clk; - int ret; - - ret = uclass_get_device(UCLASS_CPU, 0, &dev); - if (ret) - return 0; - - ret = clk_get_by_index(dev, 0, &cpu_clk); - if (ret) { - dev_err(dev, "failed to clk\n"); - return 0; - } - - u32 cpurev; - - cpurev = get_cpu_rev(); - - printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n", - get_imx8_type((cpurev & 0xFF000) >> 12), - get_imx8_rev((cpurev & 0xFFF)), - get_core_name(), - clk_get_rate(&cpu_clk) / 1000000); - - return 0; -} -#endif - #define BT_PASSOVER_TAG 0x504F struct pass_over_info_t *get_pass_over_info(void) { @@ -581,3 +506,141 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) err: printf("%s: fuse %d, err: %d\n", __func__, word[i], ret); } + +#if CONFIG_IS_ENABLED(CPU) +struct cpu_imx_platdata { + const char *name; + const char *rev; + const char *type; + u32 cpurev; + u32 freq_mhz; +}; + +u32 get_cpu_rev(void) +{ + u32 id = 0, rev = 0; + int ret; + + ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id); + if (ret) + return 0; + + rev = (id >> 5) & 0xf; + id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ + + return (id << 12) | rev; +} + +const char *get_imx8_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX8QXP: + case MXC_CPU_IMX8QXP_A0: + return "QXP"; + default: + return "??"; + } +} + +const char *get_imx8_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_A: + return "A"; + case CHIP_REV_B: + return "B"; + default: + return "?"; + } +} + +const char *get_core_name(void) +{ + if (is_cortex_a35()) + return "A35"; + else if (is_cortex_a53()) + return "A53"; + else if (is_cortex_a72()) + return "A72"; + else + return "?"; +} + +int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) +{ + struct cpu_imx_platdata *plat = dev_get_platdata(dev); + + if (size < 100) + return -ENOSPC; + + snprintf(buf, size, "CPU: Freescale i.MX8%s Rev%s %s at %u MHz\n", + plat->type, plat->rev, plat->name, plat->freq_mhz); + + return 0; +} + +static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info) +{ + struct cpu_imx_platdata *plat = dev_get_platdata(dev); + + info->cpu_freq = plat->freq_mhz * 1000; + info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU); + return 0; +} + +static int cpu_imx_get_count(struct udevice *dev) +{ + return 4; +} + +static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size) +{ + snprintf(buf, size, "NXP"); + return 0; +} + +static const struct cpu_ops cpu_imx8_ops = { + .get_desc = cpu_imx_get_desc, + .get_info = cpu_imx_get_info, + .get_count = cpu_imx_get_count, + .get_vendor = cpu_imx_get_vendor, +}; + +static const struct udevice_id cpu_imx8_ids[] = { + { .compatible = "arm,cortex-a35" }, + { } +}; + +static int imx8_cpu_probe(struct udevice *dev) +{ + struct cpu_imx_platdata *plat = dev_get_platdata(dev); + struct clk cpu_clk; + u32 cpurev; + int ret; + + cpurev = get_cpu_rev(); + plat->cpurev = cpurev; + plat->name = get_core_name(); + plat->rev = get_imx8_rev(cpurev & 0xFFF); + plat->type = get_imx8_type((cpurev & 0xFF000) >> 12); + + ret = clk_get_by_index(dev, 0, &cpu_clk); + if (ret) { + debug("%s: Failed to get CPU clk: %d\n", __func__, ret); + return 0; + } + + plat->freq_mhz = clk_get_rate(&cpu_clk) / 1000000; + return 0; +} + +U_BOOT_DRIVER(cpu_imx8_drv) = { + .name = "imx8x_cpu", + .id = UCLASS_CPU, + .of_match = cpu_imx8_ids, + .ops = &cpu_imx8_ops, + .probe = imx8_cpu_probe, + .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata), + .flags = DM_FLAG_PRE_RELOC, +}; +#endif -- cgit v1.2.3 From abeebc19dbe0445793dab45d48dc60541e58fe6a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:25 +0200 Subject: imx8: add iomux configuration api Add iomux configuration api. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/iomux.h | 40 +++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/iomux.c | 43 ++++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 arch/arm/mach-imx/imx8/iomux.c (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/iomux.h b/arch/arm/include/asm/arch-imx8/iomux.h new file mode 100644 index 0000000000..bedd01bfd8 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/iomux.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_IOMUX_H__ +#define __ASM_ARCH_IMX8_IOMUX_H__ + +/* + * We use 64bits value for iomux settings. + * High 32bits are used for padring register value, + * low 16bits are used for pin index. + */ +typedef u64 iomux_cfg_t; + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK BIT(31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK BIT(30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK GENMASK(29, 27) +#define PADRING_CONFIG_SHIFT 25 +#define PADRING_LPCONFIG_SHIFT 23 +#define PADRING_PULL_SHIFT 5 +#define PADRING_DSE_SHIFT 0 + +#define MUX_PAD_CTRL_SHIFT 32 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT) +#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF) + +/* Valid mux alt0 to alt7 */ +#define MUX_MODE_ALT(x) (((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \ + MUX_MODE_MASK) + +void imx8_iomux_setup_pad(iomux_cfg_t pad); +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count); +#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */ diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 57876139a1..31ad169ccf 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o +obj-y += cpu.o iomux.o diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c new file mode 100644 index 0000000000..0ade85fb8f --- /dev/null +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * configures a single pad in the iomuxer + */ +void imx8_iomux_setup_pad(iomux_cfg_t pad) +{ + sc_pad_t pin_id = pad & PIN_ID_MASK; + int ret; + + u32 val = (u32)((pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT); + + val |= PADRING_IFMUX_EN_MASK; + val |= PADRING_GP_EN_MASK; + + ret = sc_pad_set(-1, pin_id, val); + if (ret) + printf("sc_pad_set failed!, pin: %u, val: 0x%x\n", pin_id, val); + + debug("iomux: pin %d, val = 0x%x\n", pin_id, val); +} + +/* configures a list of pads within declared with IOMUX_PADS macro */ +void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count) +{ + iomux_cfg_t const *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + imx8_iomux_setup_pad(*p); + p++; + } +} -- cgit v1.2.3 From 2d58296f3ec93b9d9ff862eb6e656af1f7cd8c47 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:26 +0200 Subject: imx8: add dummy clock This driver is mostly used to avoid build errors. We use uclass clk driver for clk related operations. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/clock.h | 27 +++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/clock.c | 21 +++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/clock.h create mode 100644 arch/arm/mach-imx/imx8/clock.c (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/clock.h b/arch/arm/include/asm/arch-imx8/clock.h new file mode 100644 index 0000000000..bea157171f --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/clock.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_CLOCK_H__ +#define __ASM_ARCH_IMX8_CLOCK_H__ + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, + MXC_FEC_CLK, +}; + +u32 mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */ diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c new file mode 100644 index 0000000000..d747e1332f --- /dev/null +++ b/arch/arm/mach-imx/imx8/clock.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + default: + printf("Unsupported mxc_clock %d\n", clk); + break; + } + + return 0; +} -- cgit v1.2.3 From 8b2a31f13362521e65ccb4c7d73db467068e8e6a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:27 +0200 Subject: gpio: mxc_gpio: add support for i.MX8 Add i.MX8 support, there are 8 GPIO banks. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/gpio.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/gpio.h b/arch/arm/include/asm/arch-imx8/gpio.h new file mode 100644 index 0000000000..24cfde3c29 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/gpio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_GPIO_H +#define __ASM_ARCH_IMX8_GPIO_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 gpio_psr; /* pad satus */ +}; +#endif + +/* IMX8 the GPIO index is from 0 not 1 */ +#define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31)) + +#endif /* __ASM_ARCH_IMX8_GPIO_H */ -- cgit v1.2.3 From d526f340f702b338389f1b858cdd114fffbcd7b5 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:29 +0200 Subject: power: Add power domain driver for i.MX8 Add the power domain DM driver for i.MX8, that it depends on the DTB power domain trees to generate the power domain provider devices. Users need to add power domain trees with property "compatible = "nxp,imx8-pd";" When power on a PD device, the driver will power on its ancestor PD devices in power domain tree. When power off a PD device, the driver will check its child PD devices first. Only if all child PD devices are off, then power off the current PD device. Then the driver checks sibling PD devices. If sibling PD devices are off, then it will power off parent PD device. There is no counter maintained in this driver, but a state to hold current on/off state. So the request and free functions are empty. The power domain implementation in i.MX8 DTB set the "#power-domain-cells" to 0, so there is no ID binding with each PD device. We don't use "id" variable in struct power_domain. At the same time, we have to set of_xlate to empty to bypass standard of_xlate in uclass driver. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/power-domain.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h new file mode 100644 index 0000000000..1396008877 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/power-domain.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 NXP + */ + +#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H +#define _ASM_ARCH_IMX8_POWER_DOMAIN_H + +#include + +struct imx8_power_domain_platdata { + sc_rsrc_t resource_id; +}; + +#endif -- cgit v1.2.3 From f180f4a482178c6d787c1ae43b5a486a2cc6c44a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:36 +0200 Subject: arm: dts: introduce dtsi for i.MX8QXP Introduce dtsi for i.MX8QXP, since there is other variants i.MX8DX(P), so add them there, because i.MX8QXP includes the dtsi of them. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin --- arch/arm/dts/fsl-imx8-ca35.dtsi | 66 ++++++ arch/arm/dts/fsl-imx8dx.dtsi | 499 ++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/fsl-imx8dxp.dtsi | 11 + arch/arm/dts/fsl-imx8qxp.dtsi | 51 ++++ 4 files changed, 627 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8-ca35.dtsi create mode 100644 arch/arm/dts/fsl-imx8dx.dtsi create mode 100644 arch/arm/dts/fsl-imx8dxp.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi (limited to 'arch') diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi new file mode 100644 index 0000000000..28bc32c8b7 --- /dev/null +++ b/arch/arm/dts/fsl-imx8-ca35.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters having 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi new file mode 100644 index 0000000000..3b1a2a20e3 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include "fsl-imx8-ca35.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model = "Freescale i.MX8DX"; + compatible = "fsl,imx8dx", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + serial0 = &lpuart0; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x2000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + decoder_rpc: decoder_rpc@0x90400000 { + no-map; + reg = <0 0x90400000 0 0x1000000>; + }; + encoder_rpc: encoder_rpc@0x91400000 { + no-map; + reg = <0 0x91400000 0 0x1000000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + decoder_str: str@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x1800000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x96000000 0 0x28000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + mu: mu@5d1c0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1c0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + status = "okay"; + + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + }; + + imx8qx-pm { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6: PD_LSIO_GPIO_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <225>; + }; + }; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C1_CLK>, + <&clk IMX8QXP_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C3_CLK>, + <&clk IMX8QXP_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = ; + clocks = <&clk IMX8QXP_UART0_CLK>, + <&clk IMX8QXP_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, + <&clk IMX8QXP_SDHC1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, + <&clk IMX8QXP_SDHC2_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, + <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>; + assigned-clock-rates = <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, + <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>; + assigned-clock-rates = <125000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd_conn_enet1>; + status = "disabled"; + }; +}; + +&A35_0 { + clocks = <&clk IMX8QXP_A35_DIV>; +}; + +/delete-node/ &A35_2; +/delete-node/ &A35_3; diff --git a/arch/arm/dts/fsl-imx8dxp.dtsi b/arch/arm/dts/fsl-imx8dxp.dtsi new file mode 100644 index 0000000000..cc688f4469 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxp.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include "fsl-imx8dx.dtsi" + +/ { + model = "Freescale i.MX8DXP"; + compatible = "fsl,imx8dxp", "fsl,imx8qxp"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp.dtsi b/arch/arm/dts/fsl-imx8qxp.dtsi new file mode 100644 index 0000000000..1bffff1314 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dxp.dtsi" + +/ { + model = "Freescale i.MX8QXP"; + compatible = "fsl,imx8qxp"; + + cpus { + A35_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + }; + + pmu { + interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>; + }; +}; + +&A35_2 { + device_type = "cpu"; +}; + +&A35_3 { + device_type = "cpu"; +}; -- cgit v1.2.3 From d0dd73974c613650cb0c3d32a734a954cedc9f8a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Oct 2018 14:28:37 +0200 Subject: imx: add i.MX8QXP MEK board support Add i.MX8QXP MEK board support Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 13 +++ 3 files changed, 261 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 44ebc50bfa..61598bdfeb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -452,6 +452,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb +dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb.dtb \ r8a7795-salvator-x.dtb \ diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts new file mode 100644 index 0000000000..09ea3b4a3a --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <3480>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_ioexp_rst: ioexp-rst-grp { + fsl,pins = < + SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + }; +}; + +&A35_0 { + u-boot,dm-pre-reloc; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + status = "okay"; + + i2cswitch@71 { + compatible = "nxp,pca9646"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + + bb_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + mfi_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2cexp1_i2c1: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2cexp2_i2c1: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 28910c1509..0d3a87cd74 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -10,4 +10,17 @@ config IMX8QXP config SYS_SOC default "imx8" +choice + prompt "i.MX8 board select" + optional + +config TARGET_IMX8QXP_MEK + bool "Support i.MX8QXP MEK board" + select BOARD_LATE_INIT + select IMX8QXP + +endchoice + +source "board/freescale/imx8qxp_mek/Kconfig" + endif -- cgit v1.2.3 From 0e5c8ce7342db9c88d59412b184c5e214c88f27c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 16 Oct 2018 04:50:35 +0000 Subject: arm: imx: include imx8image support When building i.MX8/8X board, use imx8image type. `-e $(CONFIG_SYS_TEXT_BASE)` is not needed, but no harm to keep it for i.MX8/8X Signed-off-by: Peng Fan --- arch/arm/mach-imx/Makefile | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d6dcbe0c7c..2d79c71371 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -86,24 +86,29 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) -MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ - -e $(CONFIG_SYS_TEXT_BASE) +IMAGE_TYPE = imximage +ifeq ($(CONFIG_ARCH_IMX8), y) +IMAGE_TYPE = imx8image +endif + +MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ + -T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE) u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) ifeq ($(CONFIG_OF_SEPARATE),y) -MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ - -e $(CONFIG_SYS_TEXT_BASE) +MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ + -T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE) u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) endif -MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ - -e $(CONFIG_SPL_TEXT_BASE) +MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ + -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) SPL: MKIMAGEOUTPUT = SPL.log SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout $(PLUGIN).bin FORCE -- cgit v1.2.3 From be277c3a89fcec9f837bf4fb562c606155b0999f Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Wed, 5 Sep 2018 11:56:05 +0100 Subject: imx: mx7: avoid some initialization if low level is skipped We can have the case where u-boot is launched after some other low level enabler, like for example when u-boot runs after arm-trusted-firmware and/or optee. So, because of that we may need to jump the initialization of some IP blocks even because we may no longer have the permission for that. So, if the config option to skip low level init is set disable also timer, board and csu initialization. Signed-off-by: Rui Miguel Silva Signed-off-by: Bryan O'Donoghue Cc: Stefano Babic Cc: Fabio Estevam Cc: Albert Aribaud Cc: Peng Fan Cc: u-boot@lists.denx.de Reviewed-by: Peng Fan --- arch/arm/mach-imx/mx7/soc.c | 2 ++ arch/arm/mach-imx/syscounter.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 502f033162..3f74f8a3ed 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -164,6 +164,7 @@ u32 __weak get_board_rev(void) } #endif +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* enable all periherial can be accessed in nosec mode */ static void init_csu(void) { @@ -285,6 +286,7 @@ int arch_cpu_init(void) return 0; } +#endif #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 676bb3caa9..2c319681fc 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -55,6 +55,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec) return usec; } +#ifndef CONFIG_SKIP_LOWLEVEL_INIT int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; @@ -76,6 +77,7 @@ int timer_init(void) return 0; } +#endif unsigned long long get_ticks(void) { -- cgit v1.2.3 From d79611598fb74dc0f7cb37d855fff28d77ba8d53 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 25 Oct 2018 08:32:40 +0000 Subject: imx: mkimage: avoid stop CI when required files not exists Introduce a new script to check whether file exists and use that check in Makefile to avoid break CI system. The script return 1 when the required files not exists, return 0 when files exists. The script will ignore check to u-boot-dtb.bin, because if there is something wrong to generate u-boot-dtb.bin, there must be some code error. Signed-off-by: Peng Fan --- arch/arm/mach-imx/Makefile | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 2d79c71371..72fe23a2b9 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -86,9 +86,13 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) -IMAGE_TYPE = imximage ifeq ($(CONFIG_ARCH_IMX8), y) -IMAGE_TYPE = imx8image +CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh +IMAGE_TYPE := imx8image +DEPFILE_EXISTS := $(shell if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) +else +IMAGE_TYPE := imximage +DEPFILE_EXISTS := 0 endif MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ @@ -104,8 +108,10 @@ MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE +ifeq ($(DEPFILE_EXISTS),0) $(call if_changed,mkimage) endif +endif MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) -- cgit v1.2.3 From 3c28576bb0f0990d699fd330089412e620706941 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 25 Oct 2018 08:36:49 +0000 Subject: arm: dts: imx8qxp: fix build warining Fix below build warning. arch/arm/dts/fsl-imx8qxp-mek.dtb: Warning (avoid_unnecessary_addr_size): /regulators: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Peng Fan --- arch/arm/dts/fsl-imx8qxp-mek.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts index 09ea3b4a3a..c14e1845a1 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek.dts +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -18,8 +18,6 @@ regulators { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; -- cgit v1.2.3