From 37118fb27be72dc7f3af27b390306396ad6d56b2 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Fri, 23 Jan 2015 15:50:04 +0530 Subject: Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas This patch adds basic constructs in the ARMv8 u-boot code to handle and apply Cortex-A57 specific erratas. As and example, the framework showcases how erratas 833069, 826974 and 828024 can be handled and applied. Later on this framework can be extended to include other erratas. Signed-off-by: Bhupesh Sharma --- arch/arm/cpu/armv8/start.S | 45 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/macro.h | 22 ++++++++++++++++++++++ 2 files changed, 67 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 4b11aa4f22..540a5db843 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -67,6 +67,9 @@ reset: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: + /* Apply ARM core specific erratas */ + bl apply_core_errata + /* * Cache/BPB/TLB Invalidate * i-cache is invalidated before enabled in icache_enable() @@ -97,6 +100,48 @@ master_cpu: /*-----------------------------------------------------------------------*/ +WEAK(apply_core_errata) + + mov x29, lr /* Save LR */ + /* For now, we support Cortex-A57 specific errata only */ + + /* Check if we are running on a Cortex-A57 core */ + branch_if_a57_core x0, apply_a57_core_errata +0: + mov lr, x29 /* Restore LR */ + ret + +apply_a57_core_errata: + +#ifdef CONFIG_ARM_ERRATA_828024 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable non-allocate hint of w-b-n-a memory type */ + mov x0, #0x1 << 49 + /* Disable write streaming no L1-allocate threshold */ + mov x0, #0x3 << 25 + /* Disable write streaming no-allocate threshold */ + mov x0, #0x3 << 27 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_826974 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable speculative load execution ahead of a DMB */ + mov x0, #0x1 << 59 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_833069 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable Enable Invalidates of BTB bit */ + and x0, x0, #0xE + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + b 0b +ENDPROC(apply_core_errata) + +/*-----------------------------------------------------------------------*/ + WEAK(lowlevel_init) mov x29, lr /* Save LR */ diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 1c8c4251ee..5f7c7e0501 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -73,6 +73,28 @@ lr .req x30 b.eq \el1_label .endm +/* + * Branch if current processor is a Cortex-A57 core. + */ +.macro branch_if_a57_core, xreg, a57_label + mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + and \xreg, \xreg, #0x00000FFF + cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */ + b.eq \a57_label +.endm + +/* + * Branch if current processor is a Cortex-A53 core. + */ +.macro branch_if_a53_core, xreg, a53_label + mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + and \xreg, \xreg, #0x00000FFF + cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */ + b.eq \a53_label +.endm + /* * Branch if current processor is a slave, * choose processor with all zero affinity value as the master. -- cgit v1.2.3 From 23d184d2fbc805bdd9fb41f2370cdce04a7894af Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 30 Jan 2015 12:04:56 -0700 Subject: arm: Show relocated PC/LR in the register dump If we don't know the relocation address, the raw values are not very useful. Show the pre-relocation values as well as these can be looked up in System.map, etc. Signed-off-by: Simon Glass Acked-by: Albert ARIBAUD --- arch/arm/lib/interrupts.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 4dacfd941f..06f46795c3 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -137,10 +137,15 @@ void show_regs (struct pt_regs *regs) flags = condition_codes (regs); - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf("pc : [<%08lx>] lr : [<%08lx>]\n", + instruction_pointer(regs), regs->ARM_lr); + if (gd->flags & GD_FLG_RELOC) { + printf("reloc pc : [<%08lx>] lr : [<%08lx>]\n", + instruction_pointer(regs) - gd->reloc_off, + regs->ARM_lr - gd->reloc_off); + } + printf("sp : %08lx ip : %08lx fp : %08lx\n", + regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", -- cgit v1.2.3 From c1b0fad9b655e0251c686cd129eb2f933fcc6b3a Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sat, 31 Jan 2015 22:49:39 +0100 Subject: edminiv2: fix PCIE IO base address typo Signed-off-by: Albert ARIBAUD --- arch/arm/mach-orion5x/include/mach/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-orion5x/include/mach/cpu.h b/arch/arm/mach-orion5x/include/mach/cpu.h index 08a450f1f3..092dbd66a1 100644 --- a/arch/arm/mach-orion5x/include/mach/cpu.h +++ b/arch/arm/mach-orion5x/include/mach/cpu.h @@ -86,7 +86,7 @@ enum orion5x_cpu_attrib { #endif #if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) -#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000 +#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000 #endif #if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) -- cgit v1.2.3 From 9608e7de6ac13626e8a2809b0350add57c1343ac Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sat, 31 Jan 2015 22:55:38 +0100 Subject: edminiv2: switch to SPL ED Mini V2 is based on Orion 5x which boots at fixed address 0xFFFF0000 in NOR Flash. Place SPL there, and switch U-Boot from .bin to .img format, stored in NOR Flash at 0xFFF90000. Note: this patch was tested on HW and works, i.e. it boots U-Boot properly, but SPL console output currently does not appear, due to GD being trashed by arch/arm/lib/spl.c. This trashing is soon to be removed, and then ED Mini V2 SPL console output will become visible. Signed-off-by: Albert ARIBAUD --- arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds | 61 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-orion5x/spl.h | 10 +++++ arch/arm/mach-orion5x/Kconfig | 1 + arch/arm/mach-orion5x/cpu.c | 2 + arch/arm/mach-orion5x/lowlevel_init.S | 14 +++++- 5 files changed, 86 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-orion5x/spl.h (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds new file mode 100644 index 0000000000..6f7fca07e3 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2014 Albert ARIBAUD + * + * Based on: + * + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Based on omap-common/u-boot-spl.lds: + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ +MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + CPUDIR/start.o (.text) + *(.text*) + } > .nor + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .nor + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .bss +} diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h new file mode 100644 index 0000000000..23745bc1a5 --- /dev/null +++ b/arch/arm/include/asm/arch-orion5x/spl.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2014 Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NOR 1 diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 5a542629c7..291c511ba8 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -5,6 +5,7 @@ choice config TARGET_EDMINIV2 bool "LaCie Ethernet Disk mini V2" + select SUPPORT_SPL endchoice diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index f88db3b1f9..2ecd385678 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -234,7 +234,9 @@ int arch_cpu_init(void) /* Enable and invalidate L2 cache in write through mode */ invalidate_l2_cache(); +#ifdef CONFIG_SPL_BUILD orion5x_config_adr_windows(); +#endif return 0; } diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 4dacc296e4..51a8b3c51b 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -62,14 +62,16 @@ /* * Low-level init happens right after start.S has switched to SVC32, * flushed and disabled caches and disabled MMU. We're still running - * from the boot chip select, so the first thing we should do is set - * up RAM for us to relocate into. + * from the boot chip select, so the first thing SPL should do is to + * set up the RAM to copy U-Boot into. */ .globl lowlevel_init lowlevel_init: +#ifdef CONFIG_SPL_BUILD + /* Use 'r4 as the base for internal register accesses */ ldr r4, =ORION5X_REGS_PHY_BASE @@ -273,5 +275,13 @@ lowlevel_init: orr r2, r2, r6 str r2, [r3, #0x484] + /* enable for 2 GB DDR; detection should find out real amount */ + sub r6, r6, r6 + str r6, [r3, #0x500] + ldr r6, =0x7fff0001 + str r6, [r3, #0x504] + +#endif /* CONFIG_SPL_BUILD */ + /* Return to U-boot via saved link register */ mov pc, lr -- cgit v1.2.3 From 02251eefc95c477f4ff6aa7568dfd4be7c69c31f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 4 Feb 2015 18:15:09 +0800 Subject: ARM: HYP/non-sec: relocation before enable secondary cores If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined, smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr( _smp_pen), before code is relocated to secure ram. So need relocation to secure ram before enable secondary cores. Signed-off-by: Peng Fan Acked-by: Marc Zyngier --- arch/arm/cpu/armv7/virt-v7.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index b69fd37c18..4cb8806238 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -112,13 +112,20 @@ int armv7_init_nonsec(void) for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); + /* + * Relocate secure section before any cpu runs in secure ram. + * smp_kick_all_cpus may enable other cores and runs into secure + * ram, so need to relocate secure section before enabling other + * cores. + */ + relocate_secure_section(); + #ifndef CONFIG_ARMV7_PSCI smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); smp_kick_all_cpus(); #endif /* call the non-sec switching code on this CPU also */ - relocate_secure_section(); secure_ram_addr(_nonsec_init)(); return 0; } -- cgit v1.2.3 From 3a2cab512c0c4d96d8210e4f729dd080bbf8c90d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 23 Dec 2014 10:34:50 -0700 Subject: ARM: tegra: fix variable naming in query_sdram_size() size_mb is used to hold a value that's sometimes KB, sometimes MB, and sometimes bytes. Use separate correctly named variables to avoid confusion here. Also fix indentation of a conditional statement. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/mach-tegra/board.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index b6a84a5774..f16fe68a66 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -32,23 +32,24 @@ enum { unsigned int query_sdram_size(void) { struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; - u32 size_mb; + u32 emem_cfg, size_bytes; - size_mb = readl(&mc->mc_emem_cfg); + emem_cfg = readl(&mc->mc_emem_cfg); #if defined(CONFIG_TEGRA20) - debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb); - size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024); + debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); + size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); #else - debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb); - size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024); + debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); + size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024 * 1024); #endif #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) /* External memory limited to 2047 MB due to IROM/HI-VEC */ - if (size_mb == SZ_2G) size_mb -= SZ_1M; + if (size_bytes == SZ_2G) + size_bytes -= SZ_1M; #endif - return size_mb; + return size_bytes; } int dram_init(void) -- cgit v1.2.3 From 56519c4f0498acdfb4dccd27bbb4b69a60cbb823 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 23 Dec 2014 10:34:51 -0700 Subject: ARM: tegra: support large RAM sizes Some systems have so much RAM that the end of RAM is beyond 4GB. An example would be a Tegra124 system (where RAM starts at 2GB physical) that has more than 2GB of RAM. In this case, we want gd->ram_size to represent the actual RAM size, so that the actual RAM size is passed to the OS. This is useful if the OS implements LPAE, and can actually use the "extra" RAM. However, we can't use get_ram_size() to verify the actual amount of RAM present on such systems, since some of the RAM can't be accesses, which confuses that function. Avoid calling get_ram_size() when the RAM size is too large for it to work correctly. It's never actually needed anyway, since there's no reason for the BCT to report the wrong RAM size. In systems with >=4GB RAM, we still need to clip the reported RAM size since U-Boot uses a 32-bit variable to represent the RAM size in bytes. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/mach-tegra/board.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index f16fe68a66..87511a31df 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -40,7 +40,27 @@ unsigned int query_sdram_size(void) size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); #else debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); - size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024 * 1024); + /* + * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits + * and will wrap. Clip the reported size to the maximum that a 32-bit + * variable can represent (rounded to a page). + */ + if (emem_cfg >= 4096) { + size_bytes = U32_MAX & ~(0x1000 - 1); + } else { + /* RAM size EMC is programmed to. */ + size_bytes = emem_cfg * 1024 * 1024; + /* + * If all RAM fits within 32-bits, it can be accessed without + * LPAE, so go test the RAM size. Otherwise, we can't access + * all the RAM, and get_ram_size() would get confused, so + * avoid using it. There's no reason we should need this + * validation step anyway. + */ + if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) + size_bytes = get_ram_size((void *)PHYS_SDRAM_1, + size_bytes); + } #endif #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) -- cgit v1.2.3 From 73c38934daa10b518b20f2d21298fc8a8226843b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Jan 2015 16:25:52 -0700 Subject: ARM: tegra: support running in non-secure mode When the CPU is in non-secure (NS) mode (when running U-Boot under a secure monitor), certain actions cannot be taken, since they would need to write to secure-only registers. One example is configuring the ARM architectural timer's CNTFRQ register. We could support this in one of two ways: 1) Compile twice, once for secure mode (in which case anything goes) and once for non-secure mode (in which case certain actions are disabled). This complicates things, since everyone needs to keep track of different U-Boot binaries for different situations. 2) Detect NS mode at run-time, and optionally skip any impossible actions. This has the advantage of a single U-Boot binary working in all cases. (2) is not possible on ARM in general, since there's no architectural way to detect secure-vs-non-secure. However, there is a Tegra-specific way to detect this. This patches uses that feature to detect secure vs. NS mode on Tegra, and uses that to: * Skip the ARM arch timer initialization. * Set/clear an environment variable so that boot scripts can take different action depending on which mode the CPU is in. This might be something like: if CPU is secure: load secure monitor code into RAM. boot secure monitor. secure monitor will restart (a new copy of) U-Boot in NS mode. else: execute normal boot process Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/ap.h | 4 ++++ arch/arm/mach-tegra/board.c | 19 +++++++++++++++++++ arch/arm/mach-tegra/clock.c | 6 +++++- 3 files changed, 28 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 5c8be94d97..ca40e4e0bc 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -74,3 +74,7 @@ static inline void config_vpr(void) { } #endif + +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +bool tegra_cpu_is_non_secure(void); +#endif diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 87511a31df..0ebaf19325 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,24 @@ enum { UART_COUNT = 5, }; +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +#if !defined(CONFIG_TEGRA124) +#error tegra_cpu_is_non_secure has only been validated on Tegra124 +#endif +bool tegra_cpu_is_non_secure(void) +{ + /* + * This register reads 0xffffffff in non-secure mode. This register + * only implements bits 31:20, so the lower bits will always read 0 in + * secure mode. Thus, the lower bits are an indicator for secure vs. + * non-secure mode. + */ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); + return (mc_s_cfg0 & 1) == 1; +} +#endif + /* Read the RAM size directly from the memory controller */ unsigned int query_sdram_size(void) { diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 11c7435505..7c274b5f99 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -573,7 +574,10 @@ void clock_init(void) debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); /* Do any special system timer/TSC setup */ - arch_timer_init(); +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) + if (!tegra_cpu_is_non_secure()) +#endif + arch_timer_init(); } static void set_avp_clock_source(u32 src) -- cgit v1.2.3 From f799b03f37743a36d53d751b3b2327c226c9e978 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 18 Feb 2015 13:27:03 -0700 Subject: ARM: tegra: add function to clear pinmux CLAMPING bit This is needed to correctly apply the new Jetson TK1 pinmux config. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 3 ++- arch/arm/mach-tegra/pinmux-common.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index da477697bf..ab764960fa 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -81,8 +81,9 @@ struct pmux_pingrp_config { }; #if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) -/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ +/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ void pinmux_set_tristate_input_clamping(void); +void pinmux_clear_tristate_input_clamping(void); #endif /* Set the mux function for a pin group */ diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 6e3ab0c14c..64baed45d5 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -94,11 +94,15 @@ void pinmux_set_tristate_input_clamping(void) { u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); - u32 val; - val = readl(reg); - val |= CLAMP_INPUTS_WHEN_TRISTATED; - writel(val, reg); + setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED); +} + +void pinmux_clear_tristate_input_clamping(void) +{ + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); + + clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED); } #endif -- cgit v1.2.3 From 9f21c1a378f89c6f4ee06e5aeea37c426fdec15f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:23 -0700 Subject: ARM: tegra: pinmux: add note re: drive group field defines Tegra's drive group registers have a remarkably inconsistent layout. The current U-Boot driver doesn't take this into account at all. Add a comment to describe the issue, so at least anyone debugging the driver will be aware of this. To solve this, we'd need to add a per-drive-group data structure describing the layout for the individual register. Since we don't set up too many drive groups in U-Boot at present, this hopefully isn't causing too much practical issue. Still, we probably need to fix this sometime. Wth Tegra210, the register layout becomes almost entirely consistent, so this problem partially solves itself over time. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/mach-tegra/pinmux-common.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 64baed45d5..0bef6e2463 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -347,6 +347,21 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, #define SCHMT_SHIFT 3 #define LPMD_SHIFT 4 #define LPMD_MASK (3 << LPMD_SHIFT) +/* + * Note that the following DRV* and SLW* defines are accurate for many drive + * groups on many SoCs. We really need a per-group data structure to solve + * this, since the fields are in different positions/sizes in different + * registers (for different groups). + * + * On Tegra30/114/124, the DRV*_SHIFT values vary. + * On Tegra30, the SLW*_SHIFT values vary. + * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values + * below are wide enough to cover the widest fields, and hopefully don't + * interfere with any other fields. + * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's + * wide enough to cover all cases, since that would cause the field to + * overlap with other fields in the narrower cases. + */ #define DRVDN_SHIFT 12 #define DRVDN_MASK (0x7F << DRVDN_SHIFT) #define DRVUP_SHIFT 20 -- cgit v1.2.3 From 7a28441f4d89cac6885a7e817e41379c83cb35aa Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:24 -0700 Subject: ARM: tegra: pinmux: simplify some defines Future SoCs have a slightly different combination of pinmux options per pin. This will be simpler to handle if we simply have one define per option, rather than grouping various options together, in combinations that don't align with future chips. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 34 ++++++++++++++-------- arch/arm/include/asm/arch-tegra114/pinmux.h | 10 +++++-- arch/arm/include/asm/arch-tegra124/pinmux.h | 10 +++++-- arch/arm/include/asm/arch-tegra30/pinmux.h | 7 +++-- arch/arm/mach-tegra/pinmux-common.c | 44 ++++++++++++++++++++--------- 5 files changed, 73 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index ab764960fa..c95c9738f3 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -23,39 +23,45 @@ enum pmux_tristate { PMUX_TRI_TRISTATE = 1, }; -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT enum pmux_pin_io { PMUX_PIN_OUTPUT = 0, PMUX_PIN_INPUT = 1, PMUX_PIN_NONE, }; +#endif +#ifdef TEGRA_PMX_PINS_HAVE_LOCK enum pmux_pin_lock { PMUX_PIN_LOCK_DEFAULT = 0, PMUX_PIN_LOCK_DISABLE, PMUX_PIN_LOCK_ENABLE, }; +#endif +#ifdef TEGRA_PMX_PINS_HAVE_OD enum pmux_pin_od { PMUX_PIN_OD_DEFAULT = 0, PMUX_PIN_OD_DISABLE, PMUX_PIN_OD_ENABLE, }; +#endif +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET enum pmux_pin_ioreset { PMUX_PIN_IO_RESET_DEFAULT = 0, PMUX_PIN_IO_RESET_DISABLE, PMUX_PIN_IO_RESET_ENABLE, }; +#endif -#ifdef TEGRA_PMX_HAS_RCV_SEL +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL enum pmux_pin_rcv_sel { PMUX_PIN_RCV_SEL_DEFAULT = 0, PMUX_PIN_RCV_SEL_NORMAL, PMUX_PIN_RCV_SEL_HIGH, }; -#endif /* TEGRA_PMX_HAS_RCV_SEL */ -#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ +#endif /* * This defines the configuration for a pin, including the function assigned, @@ -68,19 +74,25 @@ struct pmux_pingrp_config { u32 func:8; /* function to assign PMUX_FUNC_... */ u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ u32 tristate:2; /* tristate or normal PMUX_TRI_... */ -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT u32 io:2; /* input or output PMUX_PIN_... */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_LOCK u32 lock:2; /* lock enable/disable PMUX_PIN... */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_OD u32 od:2; /* open-drain or push-pull driver */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET u32 ioreset:2; /* input/output reset PMUX_PIN... */ -#ifdef TEGRA_PMX_HAS_RCV_SEL +#endif +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL u32 rcv_sel:2; /* select between High and Normal */ /* VIL/VIH receivers */ #endif -#endif }; -#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ void pinmux_set_tristate_input_clamping(void); void pinmux_clear_tristate_input_clamping(void); @@ -98,7 +110,7 @@ void pinmux_tristate_enable(enum pmux_pingrp pin); /* Set a pin group to normal (non tristate) */ void pinmux_tristate_disable(enum pmux_pingrp pin); -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT /* Set a pin group as input or output */ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); #endif @@ -112,7 +124,7 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, int len); -#ifdef TEGRA_PMX_HAS_DRVGRPS +#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS #define PMUX_SLWF_MIN 0 #define PMUX_SLWF_MAX 3 @@ -176,7 +188,7 @@ struct pmux_drvgrp_config { void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, int len); -#endif /* TEGRA_PMX_HAS_DRVGRPS */ +#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ struct pmux_pingrp_desc { u8 funcs[4]; diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index b86562ac6d..06a7572f0d 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -313,9 +313,13 @@ enum pmux_func { PMUX_FUNC_COUNT, }; -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC -#define TEGRA_PMX_HAS_RCV_SEL -#define TEGRA_PMX_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_IO_RESET +#define TEGRA_PMX_PINS_HAVE_RCV_SEL #include #endif /* _TEGRA114_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 1884935a57..c440f9fe5a 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -335,9 +335,13 @@ enum pmux_func { PMUX_FUNC_COUNT, }; -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC -#define TEGRA_PMX_HAS_RCV_SEL -#define TEGRA_PMX_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_IO_RESET +#define TEGRA_PMX_PINS_HAVE_RCV_SEL #include #endif /* _TEGRA124_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index a42e00990f..e9046ff36f 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -391,8 +391,11 @@ enum pmux_func { PMUX_FUNC_COUNT, }; -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC -#define TEGRA_PMX_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_IO_RESET #include #endif /* _TEGRA30_PINMUX_H_ */ diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 0bef6e2463..5d4d2e9c30 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -24,31 +24,37 @@ #define pmux_pin_tristate_isvalid(tristate) \ (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE)) -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT /* return 1 if a pin_io_is in range */ #define pmux_pin_io_isvalid(io) \ (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT)) +#endif +#ifdef TEGRA_PMX_PINS_HAVE_LOCK /* return 1 if a pin_lock is in range */ #define pmux_pin_lock_isvalid(lock) \ (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE)) +#endif +#ifdef TEGRA_PMX_PINS_HAVE_OD /* return 1 if a pin_od is in range */ #define pmux_pin_od_isvalid(od) \ (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE)) +#endif +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET /* return 1 if a pin_ioreset_is in range */ #define pmux_pin_ioreset_isvalid(ioreset) \ (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) +#endif -#ifdef TEGRA_PMX_HAS_RCV_SEL +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL /* return 1 if a pin_rcv_sel_is in range */ #define pmux_pin_rcv_sel_isvalid(rcv_sel) \ (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) -#endif /* TEGRA_PMX_HAS_RCV_SEL */ -#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ +#endif #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset)) @@ -86,7 +92,7 @@ #define IO_RESET_SHIFT 8 #define RCV_SEL_SHIFT 9 -#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING /* This register/field only exists on Tegra114 and later */ #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40 #define CLAMP_INPUTS_WHEN_TRISTATED 1 @@ -180,7 +186,7 @@ void pinmux_tristate_disable(enum pmux_pingrp pin) pinmux_set_tristate(pin, PMUX_TRI_NORMAL); } -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) { u32 *reg = REG(pin); @@ -200,7 +206,9 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) val &= ~(1 << IO_SHIFT); writel(val, reg); } +#endif +#ifdef TEGRA_PMX_PINS_HAVE_LOCK static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) { u32 *reg = REG(pin); @@ -225,7 +233,9 @@ static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) return; } +#endif +#ifdef TEGRA_PMX_PINS_HAVE_OD static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) { u32 *reg = REG(pin); @@ -247,7 +257,9 @@ static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) return; } +#endif +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET static void pinmux_set_ioreset(enum pmux_pingrp pin, enum pmux_pin_ioreset ioreset) { @@ -270,8 +282,9 @@ static void pinmux_set_ioreset(enum pmux_pingrp pin, return; } +#endif -#ifdef TEGRA_PMX_HAS_RCV_SEL +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL static void pinmux_set_rcv_sel(enum pmux_pingrp pin, enum pmux_pin_rcv_sel rcv_sel) { @@ -294,8 +307,7 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin, return; } -#endif /* TEGRA_PMX_HAS_RCV_SEL */ -#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ +#endif static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) { @@ -304,14 +316,20 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) pinmux_set_func(pin, config->func); pinmux_set_pullupdown(pin, config->pull); pinmux_set_tristate(pin, config->tristate); -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT pinmux_set_io(pin, config->io); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_LOCK pinmux_set_lock(pin, config->lock); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_OD pinmux_set_od(pin, config->od); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET pinmux_set_ioreset(pin, config->ioreset); -#ifdef TEGRA_PMX_HAS_RCV_SEL - pinmux_set_rcv_sel(pin, config->rcv_sel); #endif +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL + pinmux_set_rcv_sel(pin, config->rcv_sel); #endif } @@ -324,7 +342,7 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, pinmux_config_pingrp(&config[i]); } -#ifdef TEGRA_PMX_HAS_DRVGRPS +#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT)) -- cgit v1.2.3 From 439f57684e9fff3209f966365a18c328f858c623 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:25 -0700 Subject: ARM: tegra: pinmux: handle feature removal on newer SoCs On some future SoCs, some of the per-drive-group features no longer exist. Add some ifdefs to support this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 12 ++++++++++++ arch/arm/include/asm/arch-tegra114/pinmux.h | 3 +++ arch/arm/include/asm/arch-tegra124/pinmux.h | 3 +++ arch/arm/include/asm/arch-tegra30/pinmux.h | 3 +++ arch/arm/mach-tegra/pinmux-common.c | 24 ++++++++++++++++++++++++ 5 files changed, 45 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index c95c9738f3..cb61aa1fa1 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -142,6 +142,7 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, #define PMUX_DRVDN_MAX 127 #define PMUX_DRVDN_NONE -1 +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD /* Defines a pin group cfg's low-power mode select */ enum pmux_lpmd { PMUX_LPMD_X8 = 0, @@ -150,20 +151,25 @@ enum pmux_lpmd { PMUX_LPMD_X, PMUX_LPMD_NONE = -1, }; +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT /* Defines whether a pin group cfg's schmidt is enabled or not */ enum pmux_schmt { PMUX_SCHMT_DISABLE = 0, PMUX_SCHMT_ENABLE = 1, PMUX_SCHMT_NONE = -1, }; +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM /* Defines whether a pin group cfg's high-speed mode is enabled or not */ enum pmux_hsm { PMUX_HSM_DISABLE = 0, PMUX_HSM_ENABLE = 1, PMUX_HSM_NONE = -1, }; +#endif /* * This defines the configuration for a pin group's pad control config @@ -174,9 +180,15 @@ struct pmux_drvgrp_config { u32 slwr:3; /* rising edge slew */ u32 drvup:8; /* pull-up drive strength */ u32 drvdn:8; /* pull-down drive strength */ +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD u32 lpmd:3; /* low-power mode selection */ +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT u32 schmt:2; /* schmidt enable */ +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM u32 hsm:2; /* high-speed mode enable */ +#endif }; /** diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 06a7572f0d..4848c95c55 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -315,6 +315,9 @@ enum pmux_func { #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_GRPS_HAVE_LPMD +#define TEGRA_PMX_GRPS_HAVE_SCHMT +#define TEGRA_PMX_GRPS_HAVE_HSM #define TEGRA_PMX_PINS_HAVE_E_INPUT #define TEGRA_PMX_PINS_HAVE_LOCK #define TEGRA_PMX_PINS_HAVE_OD diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index c440f9fe5a..4e6b88ec0e 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -337,6 +337,9 @@ enum pmux_func { #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_GRPS_HAVE_LPMD +#define TEGRA_PMX_GRPS_HAVE_SCHMT +#define TEGRA_PMX_GRPS_HAVE_HSM #define TEGRA_PMX_PINS_HAVE_E_INPUT #define TEGRA_PMX_PINS_HAVE_LOCK #define TEGRA_PMX_PINS_HAVE_OD diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index e9046ff36f..56117a4b1b 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -392,6 +392,9 @@ enum pmux_func { }; #define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_GRPS_HAVE_LPMD +#define TEGRA_PMX_GRPS_HAVE_SCHMT +#define TEGRA_PMX_GRPS_HAVE_HSM #define TEGRA_PMX_PINS_HAVE_E_INPUT #define TEGRA_PMX_PINS_HAVE_LOCK #define TEGRA_PMX_PINS_HAVE_OD diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 5d4d2e9c30..f24e8c4c50 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -352,19 +352,31 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, #define pmux_drv_isvalid(drv) \ (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX)) +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD #define pmux_lpmd_isvalid(lpm) \ (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT #define pmux_schmt_isvalid(schmt) \ (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE)) +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM #define pmux_hsm_isvalid(hsm) \ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM #define HSM_SHIFT 2 +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT #define SCHMT_SHIFT 3 +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD #define LPMD_SHIFT 4 #define LPMD_MASK (3 << LPMD_SHIFT) +#endif /* * Note that the following DRV* and SLW* defines are accurate for many drive * groups on many SoCs. We really need a per-group data structure to solve @@ -473,6 +485,7 @@ static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn) return; } +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd) { u32 *reg = DRV_REG(grp); @@ -493,7 +506,9 @@ static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd) return; } +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt) { u32 *reg = DRV_REG(grp); @@ -516,7 +531,9 @@ static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt) return; } +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm) { u32 *reg = DRV_REG(grp); @@ -539,6 +556,7 @@ static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm) return; } +#endif static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config) { @@ -548,9 +566,15 @@ static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config) pinmux_set_drvdn_slwr(grp, config->slwr); pinmux_set_drvup(grp, config->drvup); pinmux_set_drvdn(grp, config->drvdn); +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD pinmux_set_lpmd(grp, config->lpmd); +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT pinmux_set_schmt(grp, config->schmt); +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM pinmux_set_hsm(grp, config->hsm); +#endif } void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, -- cgit v1.2.3 From bc13472867beaf350b569a98c49a102476537e4f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:26 -0700 Subject: ARM: tegra: pinmux: move some type definitions On some future SoCs, some per-drive-group features became per-pin features. Move all type definitions early in the header so they can be enabled irrespective of the setting of TEGRA_PMX_SOC_HAS_DRVGRPS. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 58 ++++++++++++++++---------------- arch/arm/mach-tegra/pinmux-common.c | 30 ++++++++--------- 2 files changed, 44 insertions(+), 44 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index cb61aa1fa1..1562fa410c 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -63,6 +63,35 @@ enum pmux_pin_rcv_sel { }; #endif +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD +/* Defines a pin group cfg's low-power mode select */ +enum pmux_lpmd { + PMUX_LPMD_X8 = 0, + PMUX_LPMD_X4, + PMUX_LPMD_X2, + PMUX_LPMD_X, + PMUX_LPMD_NONE = -1, +}; +#endif + +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pmux_schmt { + PMUX_SCHMT_DISABLE = 0, + PMUX_SCHMT_ENABLE = 1, + PMUX_SCHMT_NONE = -1, +}; +#endif + +#ifdef TEGRA_PMX_GRPS_HAVE_HSM +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pmux_hsm { + PMUX_HSM_DISABLE = 0, + PMUX_HSM_ENABLE = 1, + PMUX_HSM_NONE = -1, +}; +#endif + /* * This defines the configuration for a pin, including the function assigned, * pull up/down settings and tristate settings. Having set up one of these @@ -142,35 +171,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, #define PMUX_DRVDN_MAX 127 #define PMUX_DRVDN_NONE -1 -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD -/* Defines a pin group cfg's low-power mode select */ -enum pmux_lpmd { - PMUX_LPMD_X8 = 0, - PMUX_LPMD_X4, - PMUX_LPMD_X2, - PMUX_LPMD_X, - PMUX_LPMD_NONE = -1, -}; -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pmux_schmt { - PMUX_SCHMT_DISABLE = 0, - PMUX_SCHMT_ENABLE = 1, - PMUX_SCHMT_NONE = -1, -}; -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_HSM -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pmux_hsm { - PMUX_HSM_DISABLE = 0, - PMUX_HSM_ENABLE = 1, - PMUX_HSM_NONE = -1, -}; -#endif - /* * This defines the configuration for a pin group's pad control config */ diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index f24e8c4c50..843c688200 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -56,6 +56,21 @@ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) #endif +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD +#define pmux_lpmd_isvalid(lpm) \ + (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) +#endif + +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT +#define pmux_schmt_isvalid(schmt) \ + (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE)) +#endif + +#ifdef TEGRA_PMX_GRPS_HAVE_HSM +#define pmux_hsm_isvalid(hsm) \ + (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) +#endif + #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset)) #if defined(CONFIG_TEGRA20) @@ -352,21 +367,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, #define pmux_drv_isvalid(drv) \ (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX)) -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD -#define pmux_lpmd_isvalid(lpm) \ - (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT -#define pmux_schmt_isvalid(schmt) \ - (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE)) -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_HSM -#define pmux_hsm_isvalid(hsm) \ - (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) -#endif - #ifdef TEGRA_PMX_GRPS_HAVE_HSM #define HSM_SHIFT 2 #endif -- cgit v1.2.3 From b2cd3d810387095e525522de6cae2716f4c20870 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:27 -0700 Subject: ARM: tegra: pinmux: partially handle varying register layouts Tegra210 moves some bits around in the pinmux registers. Update the code to handle this. This doesn't attempt to address the issues with the group-to-group varying drive group register layout mentioned earlier. This patch handles the SoC-to-SoC differences in the mux register layout. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/mach-tegra/pinmux-common.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 843c688200..1730d20312 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -101,11 +101,23 @@ #define DRV_REG(group) _R(0x868 + ((group) * 4)) +/* + * We could force arch-tegraNN/pinmux.h to define all of these. However, + * that's a lot of defines, and for now it's manageable to just put a + * special case here. It's possible this decision will change with future + * SoCs. + */ +#ifdef CONFIG_TEGRA210 +#define IO_SHIFT 6 +#define LOCK_SHIFT 7 +#define OD_SHIFT 11 +#else #define IO_SHIFT 5 #define OD_SHIFT 6 #define LOCK_SHIFT 7 #define IO_RESET_SHIFT 8 #define RCV_SEL_SHIFT 9 +#endif #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING /* This register/field only exists on Tegra114 and later */ -- cgit v1.2.3 From f2c60eed513ecc142e0a39373d5c16a14f976d6d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:28 -0700 Subject: ARM: tegra: pinmux: support hsm/schmitt on pins T210 support HSM and Schmitt options in the pinmux register (previous chips placed these options in the drive group register). Update the code to handle this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 10 ++++- arch/arm/mach-tegra/pinmux-common.c | 66 +++++++++++++++++++++++++++++++- 2 files changed, 72 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 1562fa410c..d87da10e0d 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -74,7 +74,7 @@ enum pmux_lpmd { }; #endif -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT +#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) /* Defines whether a pin group cfg's schmidt is enabled or not */ enum pmux_schmt { PMUX_SCHMT_DISABLE = 0, @@ -83,7 +83,7 @@ enum pmux_schmt { }; #endif -#ifdef TEGRA_PMX_GRPS_HAVE_HSM +#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) /* Defines whether a pin group cfg's high-speed mode is enabled or not */ enum pmux_hsm { PMUX_HSM_DISABLE = 0, @@ -119,6 +119,12 @@ struct pmux_pingrp_config { u32 rcv_sel:2; /* select between High and Normal */ /* VIL/VIH receivers */ #endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT + u32 schmt:2; /* schmitt enable */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_HSM + u32 hsm:2; /* high-speed mode enable */ +#endif }; #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 1730d20312..b4ed153a2e 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -61,12 +61,12 @@ (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) #endif -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT +#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) #define pmux_schmt_isvalid(schmt) \ (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE)) #endif -#ifdef TEGRA_PMX_GRPS_HAVE_HSM +#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) #define pmux_hsm_isvalid(hsm) \ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) #endif @@ -110,7 +110,13 @@ #ifdef CONFIG_TEGRA210 #define IO_SHIFT 6 #define LOCK_SHIFT 7 +#ifdef TEGRA_PMX_PINS_HAVE_HSM +#define HSM_SHIFT 9 +#endif #define OD_SHIFT 11 +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT +#define SCHMT_SHIFT 12 +#endif #else #define IO_SHIFT 5 #define OD_SHIFT 6 @@ -336,6 +342,56 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin, } #endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT +static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt) +{ + u32 *reg = REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (schmt == PMUX_SCHMT_NONE) + return; + + /* Error check pad */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_schmt_isvalid(schmt)); + + val = readl(reg); + if (schmt == PMUX_SCHMT_ENABLE) + val |= (1 << SCHMT_SHIFT); + else + val &= ~(1 << SCHMT_SHIFT); + writel(val, reg); + + return; +} +#endif + +#ifdef TEGRA_PMX_PINS_HAVE_HSM +static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm) +{ + u32 *reg = REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (hsm == PMUX_HSM_NONE) + return; + + /* Error check pad */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_hsm_isvalid(hsm)); + + val = readl(reg); + if (hsm == PMUX_HSM_ENABLE) + val |= (1 << HSM_SHIFT); + else + val &= ~(1 << HSM_SHIFT); + writel(val, reg); + + return; +} +#endif + static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) { enum pmux_pingrp pin = config->pingrp; @@ -358,6 +414,12 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL pinmux_set_rcv_sel(pin, config->rcv_sel); #endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT + pinmux_set_schmt(pin, config->schmt); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_HSM + pinmux_set_hsm(pin, config->hsm); +#endif } void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, -- cgit v1.2.3 From 790f7719e2635a3ff3f44473b060e01b5b5ebf74 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:29 -0700 Subject: ARM: tegra: pinmux: account for different drivegroup base registers Tegra210 starts its drive group registers at a different offset from the APB MISC register block that other SoCs. Update the code to handle this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra114/pinmux.h | 1 + arch/arm/include/asm/arch-tegra124/pinmux.h | 1 + arch/arm/include/asm/arch-tegra20/pinmux.h | 1 + arch/arm/include/asm/arch-tegra30/pinmux.h | 1 + arch/arm/mach-tegra/pinmux-common.c | 2 +- 5 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 4848c95c55..38d8b9cf4d 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -313,6 +313,7 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS #define TEGRA_PMX_GRPS_HAVE_LPMD diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 4e6b88ec0e..78bc9e6f17 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -335,6 +335,7 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS #define TEGRA_PMX_GRPS_HAVE_LPMD diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index f7bc97fe5f..bf35d50ba3 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -233,6 +233,7 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #include #endif /* _TEGRA20_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 56117a4b1b..3358bf7ce3 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -391,6 +391,7 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_DRVGRPS #define TEGRA_PMX_GRPS_HAVE_LPMD #define TEGRA_PMX_GRPS_HAVE_SCHMT diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index b4ed153a2e..9bf3086971 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -99,7 +99,7 @@ #endif /* CONFIG_TEGRA20 */ -#define DRV_REG(group) _R(0x868 + ((group) * 4)) +#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4)) /* * We could force arch-tegraNN/pinmux.h to define all of these. However, -- cgit v1.2.3 From f4d7c9dd443b7c736304dd2b80b82a7b6074a25a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:30 -0700 Subject: ARM: tegra: pinmux: support Tegra210's e_io_hv pin option Tegra210 has a per-pin option named e_io_hv, which indicates that the pin's input path should be configured to be 3.3v-tolerant. Add support for this. Note that this is very similar to previous chip's rcv_sel option. However, since the Tegra TRM names this option differently for the different chips, we support the new name so that the code exactly matches the naming in the TRM, to avoid confusion. This patch incorporates a few fixes from Tom Warren . Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 11 ++++++++++ arch/arm/mach-tegra/pinmux-common.c | 36 ++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index d87da10e0d..4212e57699 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -63,6 +63,14 @@ enum pmux_pin_rcv_sel { }; #endif +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV +enum pmux_pin_e_io_hv { + PMUX_PIN_E_IO_HV_DEFAULT = 0, + PMUX_PIN_E_IO_HV_NORMAL, + PMUX_PIN_E_IO_HV_HIGH, +}; +#endif + #ifdef TEGRA_PMX_GRPS_HAVE_LPMD /* Defines a pin group cfg's low-power mode select */ enum pmux_lpmd { @@ -119,6 +127,9 @@ struct pmux_pingrp_config { u32 rcv_sel:2; /* select between High and Normal */ /* VIL/VIH receivers */ #endif +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV + u32 e_io_hv:2; /* select 3.3v tolerant receivers */ +#endif #ifdef TEGRA_PMX_PINS_HAVE_SCHMT u32 schmt:2; /* schmitt enable */ #endif diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 9bf3086971..912f65e98b 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -56,6 +56,13 @@ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) #endif +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV +/* return 1 if a pin_e_io_hv is in range */ +#define pmux_pin_e_io_hv_isvalid(e_io_hv) \ + (((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \ + ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH)) +#endif + #ifdef TEGRA_PMX_GRPS_HAVE_LPMD #define pmux_lpmd_isvalid(lpm) \ (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) @@ -113,6 +120,7 @@ #ifdef TEGRA_PMX_PINS_HAVE_HSM #define HSM_SHIFT 9 #endif +#define E_IO_HV_SHIFT 10 #define OD_SHIFT 11 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT #define SCHMT_SHIFT 12 @@ -342,6 +350,31 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin, } #endif +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV +static void pinmux_set_e_io_hv(enum pmux_pingrp pin, + enum pmux_pin_e_io_hv e_io_hv) +{ + u32 *reg = REG(pin); + u32 val; + + if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT) + return; + + /* Error check on pin and e_io_hv */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_e_io_hv_isvalid(e_io_hv)); + + val = readl(reg); + if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH) + val |= (1 << E_IO_HV_SHIFT); + else + val &= ~(1 << E_IO_HV_SHIFT); + writel(val, reg); + + return; +} +#endif + #ifdef TEGRA_PMX_PINS_HAVE_SCHMT static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt) { @@ -414,6 +447,9 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL pinmux_set_rcv_sel(pin, config->rcv_sel); #endif +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV + pinmux_set_e_io_hv(pin, config->e_io_hv); +#endif #ifdef TEGRA_PMX_PINS_HAVE_SCHMT pinmux_set_schmt(pin, config->schmt); #endif -- cgit v1.2.3 From 27e780f15b9ad9446f24cfa91aab94b14eab4e93 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 24 Feb 2015 14:08:31 -0700 Subject: ARM: tegra: pinmux: add Tegra210 support This patch incorporates a few fixes from Tom Warren . Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/cpu/tegra210-common/pinmux.c | 195 +++++++++++++ arch/arm/include/asm/arch-tegra210/pinmux.h | 416 ++++++++++++++++++++++++++++ 2 files changed, 611 insertions(+) create mode 100644 arch/arm/cpu/tegra210-common/pinmux.c create mode 100644 arch/arm/include/asm/arch-tegra210/pinmux.h (limited to 'arch') diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/cpu/tegra210-common/pinmux.c new file mode 100644 index 0000000000..a29c76b1fa --- /dev/null +++ b/arch/arm/cpu/tegra210-common/pinmux.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define PIN(pin, f0, f1, f2, f3) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + PMUX_FUNC_##f2, \ + PMUX_FUNC_##f3, \ + }, \ + } + +#define PIN_RESERVED {} + +static const struct pmux_pingrp_desc tegra210_pingroups[] = { + /* pin, f0, f1, f2, f3 */ + /* Offset 0x3000 */ + PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x301c */ + PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x3038 */ + PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), + PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), + PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x30a4 */ + PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), + PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), + PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), + PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), + PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), + PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), + PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), + PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), + PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), + PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), + PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), + PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), + PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), + PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), + PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), + PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), + PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), + PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), + PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), + PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), + PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), + PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), + PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), + PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), + PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), + PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), + PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), + PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), + PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), + PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), + PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), + PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), + PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), + PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), + PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), + PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), + PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), +}; +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h new file mode 100644 index 0000000000..af3b55f0d7 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/pinmux.h @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_PINMUX_H_ +#define _TEGRA210_PINMUX_H_ + +enum pmux_pingrp { + PMUX_PINGRP_SDMMC1_CLK_PM0, + PMUX_PINGRP_SDMMC1_CMD_PM1, + PMUX_PINGRP_SDMMC1_DAT3_PM2, + PMUX_PINGRP_SDMMC1_DAT2_PM3, + PMUX_PINGRP_SDMMC1_DAT1_PM4, + PMUX_PINGRP_SDMMC1_DAT0_PM5, + PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4), + PMUX_PINGRP_SDMMC3_CMD_PP1, + PMUX_PINGRP_SDMMC3_DAT0_PP5, + PMUX_PINGRP_SDMMC3_DAT1_PP4, + PMUX_PINGRP_SDMMC3_DAT2_PP3, + PMUX_PINGRP_SDMMC3_DAT3_PP2, + PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4), + PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1, + PMUX_PINGRP_PEX_WAKE_N_PA2, + PMUX_PINGRP_PEX_L1_RST_N_PA3, + PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4, + PMUX_PINGRP_SATA_LED_ACTIVE_PA5, + PMUX_PINGRP_SPI1_MOSI_PC0, + PMUX_PINGRP_SPI1_MISO_PC1, + PMUX_PINGRP_SPI1_SCK_PC2, + PMUX_PINGRP_SPI1_CS0_PC3, + PMUX_PINGRP_SPI1_CS1_PC4, + PMUX_PINGRP_SPI2_MOSI_PB4, + PMUX_PINGRP_SPI2_MISO_PB5, + PMUX_PINGRP_SPI2_SCK_PB6, + PMUX_PINGRP_SPI2_CS0_PB7, + PMUX_PINGRP_SPI2_CS1_PDD0, + PMUX_PINGRP_SPI4_MOSI_PC7, + PMUX_PINGRP_SPI4_MISO_PD0, + PMUX_PINGRP_SPI4_SCK_PC5, + PMUX_PINGRP_SPI4_CS0_PC6, + PMUX_PINGRP_QSPI_SCK_PEE0, + PMUX_PINGRP_QSPI_CS_N_PEE1, + PMUX_PINGRP_QSPI_IO0_PEE2, + PMUX_PINGRP_QSPI_IO1_PEE3, + PMUX_PINGRP_QSPI_IO2_PEE4, + PMUX_PINGRP_QSPI_IO3_PEE5, + PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4), + PMUX_PINGRP_DMIC1_DAT_PE1, + PMUX_PINGRP_DMIC2_CLK_PE2, + PMUX_PINGRP_DMIC2_DAT_PE3, + PMUX_PINGRP_DMIC3_CLK_PE4, + PMUX_PINGRP_DMIC3_DAT_PE5, + PMUX_PINGRP_GEN1_I2C_SCL_PJ1, + PMUX_PINGRP_GEN1_I2C_SDA_PJ0, + PMUX_PINGRP_GEN2_I2C_SCL_PJ2, + PMUX_PINGRP_GEN2_I2C_SDA_PJ3, + PMUX_PINGRP_GEN3_I2C_SCL_PF0, + PMUX_PINGRP_GEN3_I2C_SDA_PF1, + PMUX_PINGRP_CAM_I2C_SCL_PS2, + PMUX_PINGRP_CAM_I2C_SDA_PS3, + PMUX_PINGRP_PWR_I2C_SCL_PY3, + PMUX_PINGRP_PWR_I2C_SDA_PY4, + PMUX_PINGRP_UART1_TX_PU0, + PMUX_PINGRP_UART1_RX_PU1, + PMUX_PINGRP_UART1_RTS_PU2, + PMUX_PINGRP_UART1_CTS_PU3, + PMUX_PINGRP_UART2_TX_PG0, + PMUX_PINGRP_UART2_RX_PG1, + PMUX_PINGRP_UART2_RTS_PG2, + PMUX_PINGRP_UART2_CTS_PG3, + PMUX_PINGRP_UART3_TX_PD1, + PMUX_PINGRP_UART3_RX_PD2, + PMUX_PINGRP_UART3_RTS_PD3, + PMUX_PINGRP_UART3_CTS_PD4, + PMUX_PINGRP_UART4_TX_PI4, + PMUX_PINGRP_UART4_RX_PI5, + PMUX_PINGRP_UART4_RTS_PI6, + PMUX_PINGRP_UART4_CTS_PI7, + PMUX_PINGRP_DAP1_FS_PB0, + PMUX_PINGRP_DAP1_DIN_PB1, + PMUX_PINGRP_DAP1_DOUT_PB2, + PMUX_PINGRP_DAP1_SCLK_PB3, + PMUX_PINGRP_DAP2_FS_PAA0, + PMUX_PINGRP_DAP2_DIN_PAA2, + PMUX_PINGRP_DAP2_DOUT_PAA3, + PMUX_PINGRP_DAP2_SCLK_PAA1, + PMUX_PINGRP_DAP4_FS_PJ4, + PMUX_PINGRP_DAP4_DIN_PJ5, + PMUX_PINGRP_DAP4_DOUT_PJ6, + PMUX_PINGRP_DAP4_SCLK_PJ7, + PMUX_PINGRP_CAM1_MCLK_PS0, + PMUX_PINGRP_CAM2_MCLK_PS1, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_CLK_32K_OUT_PY5, + PMUX_PINGRP_BATT_BCL, + PMUX_PINGRP_CLK_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_SHUTDOWN, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_AUD_MCLK_PBB0, + PMUX_PINGRP_DVFS_PWM_PBB1, + PMUX_PINGRP_DVFS_CLK_PBB2, + PMUX_PINGRP_GPIO_X1_AUD_PBB3, + PMUX_PINGRP_GPIO_X3_AUD_PBB4, + PMUX_PINGRP_PCC7, + PMUX_PINGRP_HDMI_CEC_PCC0, + PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1, + PMUX_PINGRP_SPDIF_OUT_PCC2, + PMUX_PINGRP_SPDIF_IN_PCC3, + PMUX_PINGRP_USB_VBUS_EN0_PCC4, + PMUX_PINGRP_USB_VBUS_EN1_PCC5, + PMUX_PINGRP_DP_HPD0_PCC6, + PMUX_PINGRP_WIFI_EN_PH0, + PMUX_PINGRP_WIFI_RST_PH1, + PMUX_PINGRP_WIFI_WAKE_AP_PH2, + PMUX_PINGRP_AP_WAKE_BT_PH3, + PMUX_PINGRP_BT_RST_PH4, + PMUX_PINGRP_BT_WAKE_AP_PH5, + PMUX_PINGRP_AP_WAKE_NFC_PH7, + PMUX_PINGRP_NFC_EN_PI0, + PMUX_PINGRP_NFC_INT_PI1, + PMUX_PINGRP_GPS_EN_PI2, + PMUX_PINGRP_GPS_RST_PI3, + PMUX_PINGRP_CAM_RST_PS4, + PMUX_PINGRP_CAM_AF_EN_PS5, + PMUX_PINGRP_CAM_FLASH_EN_PS6, + PMUX_PINGRP_CAM1_PWDN_PS7, + PMUX_PINGRP_CAM2_PWDN_PT0, + PMUX_PINGRP_CAM1_STROBE_PT1, + PMUX_PINGRP_LCD_TE_PY2, + PMUX_PINGRP_LCD_BL_PWM_PV0, + PMUX_PINGRP_LCD_BL_EN_PV1, + PMUX_PINGRP_LCD_RST_PV2, + PMUX_PINGRP_LCD_GPIO1_PV3, + PMUX_PINGRP_LCD_GPIO2_PV4, + PMUX_PINGRP_AP_READY_PV5, + PMUX_PINGRP_TOUCH_RST_PV6, + PMUX_PINGRP_TOUCH_CLK_PV7, + PMUX_PINGRP_MODEM_WAKE_AP_PX0, + PMUX_PINGRP_TOUCH_INT_PX1, + PMUX_PINGRP_MOTION_INT_PX2, + PMUX_PINGRP_ALS_PROX_INT_PX3, + PMUX_PINGRP_TEMP_ALERT_PX4, + PMUX_PINGRP_BUTTON_POWER_ON_PX5, + PMUX_PINGRP_BUTTON_VOL_UP_PX6, + PMUX_PINGRP_BUTTON_VOL_DOWN_PX7, + PMUX_PINGRP_BUTTON_SLIDE_SW_PY0, + PMUX_PINGRP_BUTTON_HOME_PY1, + PMUX_PINGRP_PA6, + PMUX_PINGRP_PE6, + PMUX_PINGRP_PE7, + PMUX_PINGRP_PH6, + PMUX_PINGRP_PK0, + PMUX_PINGRP_PK1, + PMUX_PINGRP_PK2, + PMUX_PINGRP_PK3, + PMUX_PINGRP_PK4, + PMUX_PINGRP_PK5, + PMUX_PINGRP_PK6, + PMUX_PINGRP_PK7, + PMUX_PINGRP_PL0, + PMUX_PINGRP_PL1, + PMUX_PINGRP_PZ0, + PMUX_PINGRP_PZ1, + PMUX_PINGRP_PZ2, + PMUX_PINGRP_PZ3, + PMUX_PINGRP_PZ4, + PMUX_PINGRP_PZ5, + PMUX_PINGRP_COUNT, +}; + +enum pmux_drvgrp { + PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4), + PMUX_DRVGRP_AP_READY, + PMUX_DRVGRP_AP_WAKE_BT, + PMUX_DRVGRP_AP_WAKE_NFC, + PMUX_DRVGRP_AUD_MCLK, + PMUX_DRVGRP_BATT_BCL, + PMUX_DRVGRP_BT_RST, + PMUX_DRVGRP_BT_WAKE_AP, + PMUX_DRVGRP_BUTTON_HOME, + PMUX_DRVGRP_BUTTON_POWER_ON, + PMUX_DRVGRP_BUTTON_SLIDE_SW, + PMUX_DRVGRP_BUTTON_VOL_DOWN, + PMUX_DRVGRP_BUTTON_VOL_UP, + PMUX_DRVGRP_CAM1_MCLK, + PMUX_DRVGRP_CAM1_PWDN, + PMUX_DRVGRP_CAM1_STROBE, + PMUX_DRVGRP_CAM2_MCLK, + PMUX_DRVGRP_CAM2_PWDN, + PMUX_DRVGRP_CAM_AF_EN, + PMUX_DRVGRP_CAM_FLASH_EN, + PMUX_DRVGRP_CAM_I2C_SCL, + PMUX_DRVGRP_CAM_I2C_SDA, + PMUX_DRVGRP_CAM_RST, + PMUX_DRVGRP_CLK_32K_IN, + PMUX_DRVGRP_CLK_32K_OUT, + PMUX_DRVGRP_CLK_REQ, + PMUX_DRVGRP_CORE_PWR_REQ, + PMUX_DRVGRP_CPU_PWR_REQ, + PMUX_DRVGRP_DAP1_DIN, + PMUX_DRVGRP_DAP1_DOUT, + PMUX_DRVGRP_DAP1_FS, + PMUX_DRVGRP_DAP1_SCLK, + PMUX_DRVGRP_DAP2_DIN, + PMUX_DRVGRP_DAP2_DOUT, + PMUX_DRVGRP_DAP2_FS, + PMUX_DRVGRP_DAP2_SCLK, + PMUX_DRVGRP_DAP4_DIN, + PMUX_DRVGRP_DAP4_DOUT, + PMUX_DRVGRP_DAP4_FS, + PMUX_DRVGRP_DAP4_SCLK, + PMUX_DRVGRP_DMIC1_CLK, + PMUX_DRVGRP_DMIC1_DAT, + PMUX_DRVGRP_DMIC2_CLK, + PMUX_DRVGRP_DMIC2_DAT, + PMUX_DRVGRP_DMIC3_CLK, + PMUX_DRVGRP_DMIC3_DAT, + PMUX_DRVGRP_DP_HPD0, + PMUX_DRVGRP_DVFS_CLK, + PMUX_DRVGRP_DVFS_PWM, + PMUX_DRVGRP_GEN1_I2C_SCL, + PMUX_DRVGRP_GEN1_I2C_SDA, + PMUX_DRVGRP_GEN2_I2C_SCL, + PMUX_DRVGRP_GEN2_I2C_SDA, + PMUX_DRVGRP_GEN3_I2C_SCL, + PMUX_DRVGRP_GEN3_I2C_SDA, + PMUX_DRVGRP_PA6, + PMUX_DRVGRP_PCC7, + PMUX_DRVGRP_PE6, + PMUX_DRVGRP_PE7, + PMUX_DRVGRP_PH6, + PMUX_DRVGRP_PK0, + PMUX_DRVGRP_PK1, + PMUX_DRVGRP_PK2, + PMUX_DRVGRP_PK3, + PMUX_DRVGRP_PK4, + PMUX_DRVGRP_PK5, + PMUX_DRVGRP_PK6, + PMUX_DRVGRP_PK7, + PMUX_DRVGRP_PL0, + PMUX_DRVGRP_PL1, + PMUX_DRVGRP_PZ0, + PMUX_DRVGRP_PZ1, + PMUX_DRVGRP_PZ2, + PMUX_DRVGRP_PZ3, + PMUX_DRVGRP_PZ4, + PMUX_DRVGRP_PZ5, + PMUX_DRVGRP_GPIO_X1_AUD, + PMUX_DRVGRP_GPIO_X3_AUD, + PMUX_DRVGRP_GPS_EN, + PMUX_DRVGRP_GPS_RST, + PMUX_DRVGRP_HDMI_CEC, + PMUX_DRVGRP_HDMI_INT_DP_HPD, + PMUX_DRVGRP_JTAG_RTCK, + PMUX_DRVGRP_LCD_BL_EN, + PMUX_DRVGRP_LCD_BL_PWM, + PMUX_DRVGRP_LCD_GPIO1, + PMUX_DRVGRP_LCD_GPIO2, + PMUX_DRVGRP_LCD_RST, + PMUX_DRVGRP_LCD_TE, + PMUX_DRVGRP_MODEM_WAKE_AP, + PMUX_DRVGRP_MOTION_INT, + PMUX_DRVGRP_NFC_EN, + PMUX_DRVGRP_NFC_INT, + PMUX_DRVGRP_PEX_L0_CLKREQ_N, + PMUX_DRVGRP_PEX_L0_RST_N, + PMUX_DRVGRP_PEX_L1_CLKREQ_N, + PMUX_DRVGRP_PEX_L1_RST_N, + PMUX_DRVGRP_PEX_WAKE_N, + PMUX_DRVGRP_PWR_I2C_SCL, + PMUX_DRVGRP_PWR_I2C_SDA, + PMUX_DRVGRP_PWR_INT_N, + PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4), + PMUX_DRVGRP_SATA_LED_ACTIVE, + PMUX_DRVGRP_SDMMC1, + PMUX_DRVGRP_SDMMC2, + PMUX_DRVGRP_SDMMC3 = (0x1dc / 4), + PMUX_DRVGRP_SDMMC4, + PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4), + PMUX_DRVGRP_SPDIF_IN, + PMUX_DRVGRP_SPDIF_OUT, + PMUX_DRVGRP_SPI1_CS0, + PMUX_DRVGRP_SPI1_CS1, + PMUX_DRVGRP_SPI1_MISO, + PMUX_DRVGRP_SPI1_MOSI, + PMUX_DRVGRP_SPI1_SCK, + PMUX_DRVGRP_SPI2_CS0, + PMUX_DRVGRP_SPI2_CS1, + PMUX_DRVGRP_SPI2_MISO, + PMUX_DRVGRP_SPI2_MOSI, + PMUX_DRVGRP_SPI2_SCK, + PMUX_DRVGRP_SPI4_CS0, + PMUX_DRVGRP_SPI4_MISO, + PMUX_DRVGRP_SPI4_MOSI, + PMUX_DRVGRP_SPI4_SCK, + PMUX_DRVGRP_TEMP_ALERT, + PMUX_DRVGRP_TOUCH_CLK, + PMUX_DRVGRP_TOUCH_INT, + PMUX_DRVGRP_TOUCH_RST, + PMUX_DRVGRP_UART1_CTS, + PMUX_DRVGRP_UART1_RTS, + PMUX_DRVGRP_UART1_RX, + PMUX_DRVGRP_UART1_TX, + PMUX_DRVGRP_UART2_CTS, + PMUX_DRVGRP_UART2_RTS, + PMUX_DRVGRP_UART2_RX, + PMUX_DRVGRP_UART2_TX, + PMUX_DRVGRP_UART3_CTS, + PMUX_DRVGRP_UART3_RTS, + PMUX_DRVGRP_UART3_RX, + PMUX_DRVGRP_UART3_TX, + PMUX_DRVGRP_UART4_CTS, + PMUX_DRVGRP_UART4_RTS, + PMUX_DRVGRP_UART4_RX, + PMUX_DRVGRP_UART4_TX, + PMUX_DRVGRP_USB_VBUS_EN0, + PMUX_DRVGRP_USB_VBUS_EN1, + PMUX_DRVGRP_WIFI_EN, + PMUX_DRVGRP_WIFI_RST, + PMUX_DRVGRP_WIFI_WAKE_AP, + PMUX_DRVGRP_COUNT, +}; + +enum pmux_func { + PMUX_FUNC_DEFAULT, + PMUX_FUNC_AUD, + PMUX_FUNC_BCL, + PMUX_FUNC_BLINK, + PMUX_FUNC_CCLA, + PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, + PMUX_FUNC_CORE, + PMUX_FUNC_CPU, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DMIC1, + PMUX_FUNC_DMIC2, + PMUX_FUNC_DMIC3, + PMUX_FUNC_DP, + PMUX_FUNC_DTV, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_I2CPMU, + PMUX_FUNC_I2CVI, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4A, + PMUX_FUNC_I2S4B, + PMUX_FUNC_I2S5A, + PMUX_FUNC_I2S5B, + PMUX_FUNC_IQC0, + PMUX_FUNC_IQC1, + PMUX_FUNC_JTAG, + PMUX_FUNC_PE, + PMUX_FUNC_PE0, + PMUX_FUNC_PE1, + PMUX_FUNC_PMI, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_QSPI, + PMUX_FUNC_SATA, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SHUTDOWN, + PMUX_FUNC_SOC, + PMUX_FUNC_SOR0, + PMUX_FUNC_SOR1, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_SYS, + PMUX_FUNC_TOUCH, + PMUX_FUNC_UART, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_USB, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + PMUX_FUNC_VIMCLK, + PMUX_FUNC_VIMCLK2, + PMUX_FUNC_RSVD0, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_COUNT, +}; + +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4 +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_E_IO_HV +#include + +#endif /* _TEGRA210_PINMUX_H_ */ -- cgit v1.2.3 From cbaeceabed47ec09477a49c4a36e4c79115e0522 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 1 Mar 2015 02:05:36 +0100 Subject: dm: tegra: dts: add aliases for spi on apalis_t30 All boards with a SPI interface have a suitable spi alias except Apalis T30. Add these missing aliases just as the following commit did for the others: d2f60f93325a "dm: tegra: dts: Add aliases for spi on tegra30 boards" Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/dts/tegra30-apalis.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 15db0f275b..75c5d5f786 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -18,6 +18,10 @@ sdhci0 = "/sdhci@78000600"; sdhci1 = "/sdhci@78000400"; sdhci2 = "/sdhci@78000000"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000dc00"; + spi2 = "/spi@7000de00"; + spi3 = "/spi@7000da00"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d004000"; usb2 = "/usb@7d008000"; -- cgit v1.2.3 From 72731118e241266b88c89bfc01a0162d0e27ff2b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 1 Mar 2015 02:05:37 +0100 Subject: apalis/colibri_t30: fix MMC/SD card detect GPIOs This fixes the MMC/SD card detect GPIOs for Apalis T30 which got broken by the following commit: 2b2b50bc8748 "dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOs" While at it also re-add the comments describing which particular Apalis/Colibri pins those GPIOs are on. Signed-off-by: Marcel Ziswiler Reviewed-by: Simon Glass Acked-by: Stefan Agner Signed-off-by: Tom Warren --- arch/arm/dts/tegra30-apalis.dts | 9 +++++++-- arch/arm/dts/tegra30-colibri.dts | 4 +++- 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 75c5d5f786..13ab42bf3d 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -247,13 +247,15 @@ sdhci@78000000 { status = "okay"; bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; }; sdhci@78000400 { status = "okay"; bus-width = <8>; - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; }; sdhci@78000600 { @@ -266,12 +268,14 @@ usb@7d000000 { status = "okay"; dr_mode = "peripheral"; + /* USBO1_EN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; }; /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ usb@7d004000 { status = "okay"; + /* USBH_EN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; phy_type = "utmi"; }; @@ -279,6 +283,7 @@ /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ usb@7d008000 { status = "okay"; + /* USBH_EN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts index 6cd1902f11..36533dc840 100644 --- a/arch/arm/dts/tegra30-colibri.dts +++ b/arch/arm/dts/tegra30-colibri.dts @@ -64,7 +64,7 @@ sdhci@78000200 { status = "okay"; bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ }; sdhci@78000600 { @@ -83,12 +83,14 @@ usb@7d004000 { status = "okay"; phy_type = "utmi"; + /* VBUS_LAN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; }; /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ usb@7d008000 { status = "okay"; + /* USBH_PEN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3