From 129adf5bf4769cd93f05e53e6aab724894c31036 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Jul 2015 10:48:14 +0200 Subject: mmc: dw_mmc: Probe the MMC from OF Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files. This patch now also removes previous temporary workaround. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pantelis Antoniou Cc: Tom Rini --- arch/arm/mach-socfpga/include/mach/dwmmc.h | 2 +- arch/arm/mach-socfpga/misc.c | 9 +-------- 2 files changed, 2 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/include/mach/dwmmc.h b/arch/arm/mach-socfpga/include/mach/dwmmc.h index 945eb646ce..e8ba901047 100644 --- a/arch/arm/mach-socfpga/include/mach/dwmmc.h +++ b/arch/arm/mach-socfpga/include/mach/dwmmc.h @@ -7,6 +7,6 @@ #ifndef _SOCFPGA_DWMMC_H_ #define _SOCFPGA_DWMMC_H_ -extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); +int socfpga_dwmmc_init(const void *blob); #endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 6128d54b18..0940cc5a4f 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -125,14 +125,7 @@ int cpu_eth_init(bd_t *bis) */ int cpu_mmc_init(bd_t *bis) { -/* - * FIXME: Temporarily define CONFIG_HPS_SDMMC_BUSWIDTH to prevent breakage - * due to missing patches in u-boot/master . The upcoming patch will - * switch this to OF probing, so this whole block will go away. - */ -#define CONFIG_HPS_SDMMC_BUSWIDTH 8 - return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, - CONFIG_HPS_SDMMC_BUSWIDTH, 0); + return socfpga_dwmmc_init(gd->fdt_blob); } #endif -- cgit v1.2.3 From 65d372c44c6fd7ba280c44704136c91a03618a27 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 24 Aug 2015 11:51:46 +0200 Subject: arm: socfpga: Assure ISWGRP 0 and 1 are inited This fix makes sure that the ISWGRP0 and ISWGRP1 registers are correctly inited. In case those registers are not initialized, it is not possible to access the registers synthesised in the FPGA through the bridges. Any such access produces data abort. Signed-off-by: Marek Vasut Cc: Dinh Nguyen --- arch/arm/mach-socfpga/reset_manager.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 1186358a71..b6beaa2f22 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -7,13 +7,16 @@ #include #include -#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) @@ -97,6 +100,9 @@ void socfpga_bridges_reset(int enable) /* brdmodrst */ writel(0xffffffff, &reset_manager_base->brg_mod_reset); } else { + writel(0, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + /* Check signal from FPGA. */ if (!fpgamgr_test_fpga_ready()) { /* FPGA not ready, do nothing. */ -- cgit v1.2.3 From dfd3dff50acc3b169787f024188fa5f7276e10d1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Aug 2015 23:23:52 +0200 Subject: arm: socfpga: Always enable OF_CONTROL and SPL_OF_CONTROL The SoCFPGA probes mostly from OF and the OF is mandatory both in U-Boot itself and U-Boot SPL. Enable it by default. Signed-off-by: Marek Vasut --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c598f5e4c1..8085a24de2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -539,6 +539,8 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select CPU_V7 select SUPPORT_SPL + select OF_CONTROL + select SPL_OF_CONTROL select DM select DM_SPI_FLASH select DM_SPI -- cgit v1.2.3 From a665b051b5a191c2b5c1c8ed238ccf7d29b7109b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Aug 2015 10:16:20 +0200 Subject: arm: socfpga: Do not call board_init_r() from board_init_f() Instead of calling board_init_r() directly from board_init_f(), just return from board_init_f(). This will make the code continue executing in crt0.S _main(), from which the board_init_r() is called. This patch aligns the SoCFPGA SPL with the correct SPL design as well as reduces the stack utilisation slightly. Signed-off-by: Marek Vasut Cc: Dinh Nguyen --- arch/arm/mach-socfpga/spl.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 13ec24bc16..775a82780f 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -180,6 +180,4 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); - - board_init_r(NULL, 0); } -- cgit v1.2.3 From 952caa289ee10c7426d28e37bb3130e95a6d6431 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2015 17:28:53 +0200 Subject: arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_cyclone5_sockit.dts | 92 ++++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/Kconfig | 7 +++ 3 files changed, 100 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3babe65505..69c2c82407 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts new file mode 100644 index 0000000000..d7c41c8353 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q00@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 690e3628aa..7520757d39 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -18,15 +18,21 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_TERASIC_SOCKIT + bool "Terasic SoCkit (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_SOC default "socfpga" @@ -34,5 +40,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT endif -- cgit v1.2.3 From d88995a82bb111de2035b90aa17e92c2c6b00ede Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Aug 2015 01:37:28 +0200 Subject: arm: socfpga: Add support for DENX MCV SoM and MCVEVK board Add support for DENX MCV SoM, which is CycloneV based and the associated DENX MCVEVK baseboard. The board can boot from eMMC. Ethernet and USB is supported. Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 53 ++++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/Kconfig | 7 +++++ 3 files changed, 61 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_mcvevk.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 69c2c82407..04a9ebc41a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts new file mode 100644 index 0000000000..e1e3d738bc --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "DENX MCVEVK"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac0; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + bus-width = <8>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 7520757d39..1244ef49a2 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -18,6 +18,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_DENX_MCVEVK + bool "DENX MCVEVK (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -27,11 +31,13 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "denx" if TARGET_SOCFPGA_DENX_MCVEVK default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_SOC @@ -40,6 +46,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT endif -- cgit v1.2.3 From 55c7a765f63ab10b9a3b8cbd38bf1483901a7b36 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 1 Sep 2015 17:41:52 -0500 Subject: arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 61 ++++++++++++++++++++++++++ arch/arm/mach-socfpga/Kconfig | 7 +++ 3 files changed, 69 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 04a9ebc41a..f2e18a5654 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644 index 0000000000..b649c9ac08 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -0,0 +1,61 @@ +/* + * Copyright Altera Corporation (C) 2015 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic DE0-Nano(Atlas)"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1244ef49a2..089280a91d 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_TERASIC_DE0_NANO + bool "Terasic DE0-Nano-Atlas (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -31,6 +35,7 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -38,6 +43,7 @@ config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_SOC @@ -46,6 +52,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT -- cgit v1.2.3