From a7f99e5dd7dfa1853dee25e0fcb761eee0fb3ad3 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Mon, 23 Apr 2018 07:59:43 +0200 Subject: riscv: Add setjmp/longjmp code To support efi_loader we need to have platform support for setjmp/longjmp. Add it here. Signed-off-by: Alexander Graf --- arch/riscv/include/asm/setjmp.h | 26 ++++++++++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/setjmp.S | 66 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 arch/riscv/include/asm/setjmp.h create mode 100644 arch/riscv/lib/setjmp.S (limited to 'arch') diff --git a/arch/riscv/include/asm/setjmp.h b/arch/riscv/include/asm/setjmp.h new file mode 100644 index 0000000000..01ad6d081f --- /dev/null +++ b/arch/riscv/include/asm/setjmp.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2018 Alexander Graf + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SETJMP_H_ +#define _SETJMP_H_ 1 + +/* + * This really should be opaque, but the EFI implementation wrongly + * assumes that a 'struct jmp_buf_data' is defined. + */ +struct jmp_buf_data { + /* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */ + unsigned long s_regs[12]; /* s0 - s11 */ + unsigned long ra; + unsigned long sp; +}; + +typedef struct jmp_buf_data jmp_buf[1]; + +int setjmp(jmp_buf jmp); +void longjmp(jmp_buf jmp, int ret); + +#endif /* _SETJMP_H_ */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 0b671f7086..2eafd71a67 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-y += interrupts.o +obj-y += setjmp.o diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S new file mode 100644 index 0000000000..103f359185 --- /dev/null +++ b/arch/riscv/lib/setjmp.S @@ -0,0 +1,66 @@ +/* + * (C) 2018 Alexander Graf + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#ifdef CONFIG_CPU_RISCV_64 +#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) +#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) +#else +#define STORE_IDX(reg, idx) sw reg, (idx*4)(a0) +#define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0) +#endif + +.pushsection .text.setjmp, "ax" +ENTRY(setjmp) + /* Preserve all callee-saved registers and the SP */ + STORE_IDX(s0, 0) + STORE_IDX(s1, 1) + STORE_IDX(s2, 2) + STORE_IDX(s3, 3) + STORE_IDX(s4, 4) + STORE_IDX(s5, 5) + STORE_IDX(s6, 6) + STORE_IDX(s7, 7) + STORE_IDX(s8, 8) + STORE_IDX(s9, 9) + STORE_IDX(s10, 10) + STORE_IDX(s11, 11) + STORE_IDX(ra, 12) + STORE_IDX(sp, 13) + li a0, 0 + ret +ENDPROC(setjmp) +.popsection + +.pushsection .text.longjmp, "ax" +ENTRY(longjmp) + LOAD_IDX(s0, 0) + LOAD_IDX(s1, 1) + LOAD_IDX(s2, 2) + LOAD_IDX(s3, 3) + LOAD_IDX(s4, 4) + LOAD_IDX(s5, 5) + LOAD_IDX(s6, 6) + LOAD_IDX(s7, 7) + LOAD_IDX(s8, 8) + LOAD_IDX(s9, 9) + LOAD_IDX(s10, 10) + LOAD_IDX(s11, 11) + LOAD_IDX(ra, 12) + LOAD_IDX(sp, 13) + + /* Move the return value in place, but return 1 if passed 0. */ + beq a1, zero, longjmp_1 + mv a0, a1 + ret + + longjmp_1: + li a0, 1 + ret +ENDPROC(longjmp) +.popsection -- cgit v1.2.3 From 6cc1a2af46c448e7d822fa4976a8d6e10fc5273b Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Mon, 23 Apr 2018 07:59:44 +0200 Subject: riscv: Enable function sections The linker can remove sections that are never addressed, so it makes a lot of sense to declare every function as an individual section. This reduces the output U-Boot code size by ~30kb for me. Signed-off-by: Alexander Graf --- arch/riscv/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index a7448e2095..f65ed8725d 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -29,5 +29,5 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ -T $(srctree)/examples/standalone/riscv.lds PLATFORM_CPPFLAGS += -ffixed-gp -fpic -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 -ffunction-sections LDFLAGS_u-boot += --gc-sections -static -pie -- cgit v1.2.3 From 493d1e88b676675e0c2a8614abcba0dcbb9befa4 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Mon, 23 Apr 2018 07:59:45 +0200 Subject: riscv: Add EFI application infrastructure The hello world binary and a few selftests require to build EFI target binaries, not just the EFI host environment. This patch adds all required files to generate an EFI binary for RISC-V. Signed-off-by: Alexander Graf --- arch/riscv/config.mk | 5 ++ arch/riscv/lib/Makefile | 11 +++ arch/riscv/lib/crt0_riscv_efi.S | 152 +++++++++++++++++++++++++++++++++++++ arch/riscv/lib/elf_riscv32_efi.lds | 70 +++++++++++++++++ arch/riscv/lib/elf_riscv64_efi.lds | 70 +++++++++++++++++ arch/riscv/lib/reloc_riscv_efi.c | 97 +++++++++++++++++++++++ 6 files changed, 405 insertions(+) create mode 100644 arch/riscv/lib/crt0_riscv_efi.S create mode 100644 arch/riscv/lib/elf_riscv32_efi.lds create mode 100644 arch/riscv/lib/elf_riscv64_efi.lds create mode 100644 arch/riscv/lib/reloc_riscv_efi.c (limited to 'arch') diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index f65ed8725d..219e66683d 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -19,10 +19,12 @@ endif ifdef CONFIG_32BIT PLATFORM_LDFLAGS += -m $(32bit-emul) +EFI_LDS := elf_riscv32_efi.lds endif ifdef CONFIG_64BIT PLATFORM_LDFLAGS += -m $(64bit-emul) +EFI_LDS := elf_riscv64_efi.lds endif CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ @@ -31,3 +33,6 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 -ffunction-sections LDFLAGS_u-boot += --gc-sections -static -pie + +EFI_CRT0 := crt0_riscv_efi.o +EFI_RELOC := reloc_riscv_efi.o diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 2eafd71a67..cc562f935a 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,3 +11,14 @@ obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-y += interrupts.o obj-y += setjmp.o + +# For building EFI apps +CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) +CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI) + +CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI) +CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI) + +extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC) +extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC) +extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S new file mode 100644 index 0000000000..498870e1be --- /dev/null +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -0,0 +1,152 @@ +/* + * crt0-efi-riscv.S - PE/COFF header for RISC-V EFI applications + * + * Copright (C) 2014 Linaro Ltd. + * Copright (C) 2018 Alexander Graf + * + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + * + * This file is inspired by arch/arm/lib/crt0_aarch64_efi.S + */ + +#include + +#if __riscv_xlen == 64 +#define SIZE_LONG 8 +#define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp) +#define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp) +#define PE_MACHINE 0x5064 +#else +#define SIZE_LONG 4 +#define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp) +#define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp) +#define PE_MACHINE 0x5032 +#endif + + + .section .text.head + + /* + * Magic "MZ" signature for PE/COFF + */ + .globl ImageBase +ImageBase: + .ascii "MZ" + .skip 58 /* 'MZ' + pad + offset == 64 */ + .long pe_header - ImageBase /* Offset to the PE header */ +pe_header: + .ascii "PE" + .short 0 +coff_header: + .short PE_MACHINE /* RISC-V 64/32-bit */ + .short 2 /* nr_sections */ + .long 0 /* TimeDateStamp */ + .long 0 /* PointerToSymbolTable */ + .long 1 /* NumberOfSymbols */ + .short section_table - optional_header /* SizeOfOptionalHeader */ + /* + * Characteristics: IMAGE_FILE_DEBUG_STRIPPED | + * IMAGE_FILE_EXECUTABLE_IMAGE | IMAGE_FILE_LINE_NUMS_STRIPPED + */ + .short 0x206 +optional_header: + .short 0x20b /* PE32+ format */ + .byte 0x02 /* MajorLinkerVersion */ + .byte 0x14 /* MinorLinkerVersion */ + .long _edata - _start /* SizeOfCode */ + .long 0 /* SizeOfInitializedData */ + .long 0 /* SizeOfUninitializedData */ + .long _start - ImageBase /* AddressOfEntryPoint */ + .long _start - ImageBase /* BaseOfCode */ + +extra_header_fields: + .quad 0 /* ImageBase */ + .long 0x20 /* SectionAlignment */ + .long 0x8 /* FileAlignment */ + .short 0 /* MajorOperatingSystemVersion */ + .short 0 /* MinorOperatingSystemVersion */ + .short 0 /* MajorImageVersion */ + .short 0 /* MinorImageVersion */ + .short 0 /* MajorSubsystemVersion */ + .short 0 /* MinorSubsystemVersion */ + .long 0 /* Win32VersionValue */ + + .long _edata - ImageBase /* SizeOfImage */ + + /* + * Everything before the kernel image is considered part of the header + */ + .long _start - ImageBase /* SizeOfHeaders */ + .long 0 /* CheckSum */ + .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ + .short 0 /* DllCharacteristics */ + .quad 0 /* SizeOfStackReserve */ + .quad 0 /* SizeOfStackCommit */ + .quad 0 /* SizeOfHeapReserve */ + .quad 0 /* SizeOfHeapCommit */ + .long 0 /* LoaderFlags */ + .long 0x6 /* NumberOfRvaAndSizes */ + + .quad 0 /* ExportTable */ + .quad 0 /* ImportTable */ + .quad 0 /* ResourceTable */ + .quad 0 /* ExceptionTable */ + .quad 0 /* CertificationTable */ + .quad 0 /* BaseRelocationTable */ + + /* Section table */ +section_table: + + /* + * The EFI application loader requires a relocation section + * because EFI applications must be relocatable. This is a + * dummy section as far as we are concerned. + */ + .ascii ".reloc" + .byte 0 + .byte 0 /* end of 0 padding of section name */ + .long 0 + .long 0 + .long 0 /* SizeOfRawData */ + .long 0 /* PointerToRawData */ + .long 0 /* PointerToRelocations */ + .long 0 /* PointerToLineNumbers */ + .short 0 /* NumberOfRelocations */ + .short 0 /* NumberOfLineNumbers */ + .long 0x42100040 /* Characteristics (section flags) */ + + + .ascii ".text" + .byte 0 + .byte 0 + .byte 0 /* end of 0 padding of section name */ + .long _edata - _start /* VirtualSize */ + .long _start - ImageBase /* VirtualAddress */ + .long _edata - _start /* SizeOfRawData */ + .long _start - ImageBase /* PointerToRawData */ + + .long 0 /* PointerToRelocations (0 for executables) */ + .long 0 /* PointerToLineNumbers (0 for executables) */ + .short 0 /* NumberOfRelocations (0 for executables) */ + .short 0 /* NumberOfLineNumbers (0 for executables) */ + .long 0xe0500020 /* Characteristics (section flags) */ + +_start: + addi sp, sp, -(SIZE_LONG * 3) + SAVE_LONG(a0, 0) + SAVE_LONG(a1, 1) + SAVE_LONG(ra, 2) + + lla a0, ImageBase + lla a1, _DYNAMIC + call _relocate + bne a0, zero, 0f + + LOAD_LONG(a1, 1) + LOAD_LONG(a0, 0) + call efi_main + + LOAD_LONG(ra, 2) + +0: addi sp, sp, (SIZE_LONG * 3) + ret diff --git a/arch/riscv/lib/elf_riscv32_efi.lds b/arch/riscv/lib/elf_riscv32_efi.lds new file mode 100644 index 0000000000..96d11985b0 --- /dev/null +++ b/arch/riscv/lib/elf_riscv32_efi.lds @@ -0,0 +1,70 @@ +/* + * U-Boot riscv32 EFI linker script + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Modified from arch/arm/lib/elf_aarch64_efi.lds + */ + +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + .text 0x0 : { + _text = .; + *(.text.head) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.srodata) + *(.rodata*) + . = ALIGN(16); + } + _etext = .; + _text_size = . - _text; + .dynamic : { *(.dynamic) } + .data : { + _data = .; + *(.sdata) + *(.data) + *(.data1) + *(.data.*) + *(.got.plt) + *(.got) + + /* + * The EFI loader doesn't seem to like a .bss section, so we + * stick it all into .data: + */ + . = ALIGN(16); + _bss = .; + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(16); + _bss_end = .; + _edata = .; + } + .rela.dyn : { *(.rela.dyn) } + .rela.plt : { *(.rela.plt) } + .rela.got : { *(.rela.got) } + .rela.data : { *(.rela.data) *(.rela.data*) } + _data_size = . - _etext; + + . = ALIGN(4096); + .dynsym : { *(.dynsym) } + . = ALIGN(4096); + .dynstr : { *(.dynstr) } + . = ALIGN(4096); + .note.gnu.build-id : { *(.note.gnu.build-id) } + /DISCARD/ : { + *(.rel.reloc) + *(.eh_frame) + *(.note.GNU-stack) + } + .comment 0 : { *(.comment) } +} diff --git a/arch/riscv/lib/elf_riscv64_efi.lds b/arch/riscv/lib/elf_riscv64_efi.lds new file mode 100644 index 0000000000..25c863de8a --- /dev/null +++ b/arch/riscv/lib/elf_riscv64_efi.lds @@ -0,0 +1,70 @@ +/* + * U-Boot riscv64 EFI linker script + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Modified from arch/arm/lib/elf_aarch64_efi.lds + */ + +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + .text 0x0 : { + _text = .; + *(.text.head) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.srodata) + *(.rodata*) + . = ALIGN(16); + } + _etext = .; + _text_size = . - _text; + .dynamic : { *(.dynamic) } + .data : { + _data = .; + *(.sdata) + *(.data) + *(.data1) + *(.data.*) + *(.got.plt) + *(.got) + + /* + * The EFI loader doesn't seem to like a .bss section, so we + * stick it all into .data: + */ + . = ALIGN(16); + _bss = .; + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(16); + _bss_end = .; + _edata = .; + } + .rela.dyn : { *(.rela.dyn) } + .rela.plt : { *(.rela.plt) } + .rela.got : { *(.rela.got) } + .rela.data : { *(.rela.data) *(.rela.data*) } + _data_size = . - _etext; + + . = ALIGN(4096); + .dynsym : { *(.dynsym) } + . = ALIGN(4096); + .dynstr : { *(.dynstr) } + . = ALIGN(4096); + .note.gnu.build-id : { *(.note.gnu.build-id) } + /DISCARD/ : { + *(.rel.reloc) + *(.eh_frame) + *(.note.GNU-stack) + } + .comment 0 : { *(.comment) } +} diff --git a/arch/riscv/lib/reloc_riscv_efi.c b/arch/riscv/lib/reloc_riscv_efi.c new file mode 100644 index 0000000000..d80ffc975c --- /dev/null +++ b/arch/riscv/lib/reloc_riscv_efi.c @@ -0,0 +1,97 @@ +/* reloc_riscv.c - position independent ELF shared object relocator + Copyright (C) 2018 Alexander Graf + Copyright (C) 2014 Linaro Ltd. + Copyright (C) 1999 Hewlett-Packard Co. + Contributed by David Mosberger . + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + * Neither the name of Hewlett-Packard Co. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ + +#include + +#include + +#if __riscv_xlen == 64 +#define Elf_Dyn Elf64_Dyn +#define Elf_Rela Elf64_Rela +#define ELF_R_TYPE ELF64_R_TYPE +#else +#define Elf_Dyn Elf32_Dyn +#define Elf_Rela Elf32_Rela +#define ELF_R_TYPE ELF32_R_TYPE +#endif + +efi_status_t _relocate(long ldbase, Elf_Dyn *dyn, efi_handle_t image, + struct efi_system_table *systab) +{ + long relsz = 0, relent = 0; + Elf_Rela *rel = 0; + unsigned long *addr; + int i; + + for (i = 0; dyn[i].d_tag != DT_NULL; ++i) { + switch (dyn[i].d_tag) { + case DT_RELA: + rel = (Elf_Rela *)((ulong)dyn[i].d_un.d_ptr + ldbase); + break; + case DT_RELASZ: + relsz = dyn[i].d_un.d_val; + break; + case DT_RELAENT: + relent = dyn[i].d_un.d_val; + break; + default: + break; + } + } + + if (!rel && relent == 0) + return EFI_SUCCESS; + + if (!rel || relent == 0) + return EFI_LOAD_ERROR; + + while (relsz > 0) { + /* apply the relocs */ + switch (ELF_R_TYPE(rel->r_info)) { + case R_RISCV_RELATIVE: + addr = (ulong *)(ldbase + rel->r_offset); + *addr = ldbase + rel->r_addend; + break; + default: + /* Panic */ + while (1) ; + } + rel = (Elf_Rela *)((char *)rel + relent); + relsz -= relent; + } + return EFI_SUCCESS; +} -- cgit v1.2.3 From b66babda459e3862230f147048a4c65419e81e07 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Mon, 23 Apr 2018 07:59:46 +0200 Subject: riscv: Add board_quiesce_devices stub This patch adds an empty stub for board_quiesce_devices() which allows boards to quiesce their devices before we boot into an OS in a platform agnostic way. Signed-off-by: Alexander Graf --- arch/riscv/include/asm/u-boot-riscv.h | 1 + arch/riscv/lib/bootm.c | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h index c4c068f9e2..49febd5881 100644 --- a/arch/riscv/include/asm/u-boot-riscv.h +++ b/arch/riscv/include/asm/u-boot-riscv.h @@ -16,5 +16,6 @@ int cleanup_before_linux(void); /* board/.../... */ int board_init(void); +void board_quiesce_devices(void); #endif /* _U_BOOT_RISCV_H_ */ diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 8ede0485d4..2610a57bbf 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -15,6 +15,10 @@ DECLARE_GLOBAL_DATA_PTR; +__weak void board_quiesce_devices(void) +{ +} + int arch_fixup_fdt(void *blob) { return 0; -- cgit v1.2.3 From 6836adbe753b241499430812ec5ef41ba61bdd83 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Mon, 28 May 2018 19:06:37 +0800 Subject: efi_loader: Enable RISC-V support We have almost all pieces needed to support RISC-V UEFI binaries in place already. The only missing piece are ELF relocations for runtime code and data. This patch adds respective support in the linker script and the runtime relocation code. It also allows users to enable the EFI_LOADER configuration switch on RISC-V platforms. Signed-off-by: Alexander Graf --- arch/riscv/cpu/nx25/u-boot.lds | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/riscv/cpu/nx25/u-boot.lds b/arch/riscv/cpu/nx25/u-boot.lds index 86ebc9f4bb..c53829a07c 100644 --- a/arch/riscv/cpu/nx25/u-boot.lds +++ b/arch/riscv/cpu/nx25/u-boot.lds @@ -37,6 +37,22 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } + . = ALIGN(4); + + .efi_runtime : { + __efi_runtime_start = .; + *(efi_runtime_text) + *(efi_runtime_data) + __efi_runtime_stop = .; + } + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.relaefi_runtime_text) + *(.relaefi_runtime_data) + __efi_runtime_rel_stop = .; + } + . = ALIGN(4); /DISCARD/ : { *(.rela.plt*) } -- cgit v1.2.3 From 7215787c4ea4b14ed2efbc9926c7ea539294a151 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 29 May 2018 14:10:06 +0800 Subject: SPDX: Convert single license tags to Linux Kernel style Fix license tags problem after apply patchs about riscv: Enable efi_loader support. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/include/asm/setjmp.h | 3 +-- arch/riscv/lib/crt0_riscv_efi.S | 3 +-- arch/riscv/lib/elf_riscv32_efi.lds | 1 + arch/riscv/lib/elf_riscv64_efi.lds | 1 + arch/riscv/lib/reloc_riscv_efi.c | 1 + arch/riscv/lib/setjmp.S | 3 +-- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/riscv/include/asm/setjmp.h b/arch/riscv/include/asm/setjmp.h index 01ad6d081f..72383d4330 100644 --- a/arch/riscv/include/asm/setjmp.h +++ b/arch/riscv/include/asm/setjmp.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2018 Alexander Graf - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _SETJMP_H_ diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 498870e1be..18f61f515a 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -1,11 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * crt0-efi-riscv.S - PE/COFF header for RISC-V EFI applications * * Copright (C) 2014 Linaro Ltd. * Copright (C) 2018 Alexander Graf * - * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause - * * This file is inspired by arch/arm/lib/crt0_aarch64_efi.S */ diff --git a/arch/riscv/lib/elf_riscv32_efi.lds b/arch/riscv/lib/elf_riscv32_efi.lds index 96d11985b0..629705fc28 100644 --- a/arch/riscv/lib/elf_riscv32_efi.lds +++ b/arch/riscv/lib/elf_riscv32_efi.lds @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * U-Boot riscv32 EFI linker script * diff --git a/arch/riscv/lib/elf_riscv64_efi.lds b/arch/riscv/lib/elf_riscv64_efi.lds index 25c863de8a..aece030c37 100644 --- a/arch/riscv/lib/elf_riscv64_efi.lds +++ b/arch/riscv/lib/elf_riscv64_efi.lds @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * U-Boot riscv64 EFI linker script * diff --git a/arch/riscv/lib/reloc_riscv_efi.c b/arch/riscv/lib/reloc_riscv_efi.c index d80ffc975c..8b4b2b1d8f 100644 --- a/arch/riscv/lib/reloc_riscv_efi.c +++ b/arch/riscv/lib/reloc_riscv_efi.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* reloc_riscv.c - position independent ELF shared object relocator Copyright (C) 2018 Alexander Graf Copyright (C) 2014 Linaro Ltd. diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 103f359185..8f5a6a23aa 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) 2018 Alexander Graf - * - * SPDX-License-Identifier: GPL-2.0+ */ #include -- cgit v1.2.3 From 6f4dd62f338e327bf2135bc72f559e27d6cab54d Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 29 May 2018 09:54:40 +0800 Subject: riscv: cpu: nx25: Rename as ax25 Andes has rearranged the product combinations. nx25 and ax25 both are RISC-V architecture cpu core. But ax25 has MMU unit inside, and nx25 is not. Cpu nx25 and platform ae250 are arranged in pairs. Cpu ax25 and platform ae350 are arranged in pairs. This patch will rename nx25 as ax25 ae250 as ae350 nx25-ae250 as ax25-ae350 including filename, variable, string and definition. Then u-boot can boot linux kernel in ae350 platform reasonably. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/Kconfig | 6 +- arch/riscv/cpu/ax25/Makefile | 8 + arch/riscv/cpu/ax25/cpu.c | 32 ++++ arch/riscv/cpu/ax25/start.S | 292 ++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/ax25/u-boot.lds | 84 +++++++++++ arch/riscv/cpu/nx25/Makefile | 8 - arch/riscv/cpu/nx25/cpu.c | 32 ---- arch/riscv/cpu/nx25/start.S | 292 ------------------------------------ arch/riscv/cpu/nx25/u-boot.lds | 84 ----------- arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/ae250.dts | 97 ------------ arch/riscv/dts/ae350.dts | 97 ++++++++++++ arch/riscv/include/asm/mach-types.h | 10 +- 13 files changed, 522 insertions(+), 522 deletions(-) create mode 100644 arch/riscv/cpu/ax25/Makefile create mode 100644 arch/riscv/cpu/ax25/cpu.c create mode 100644 arch/riscv/cpu/ax25/start.S create mode 100644 arch/riscv/cpu/ax25/u-boot.lds delete mode 100644 arch/riscv/cpu/nx25/Makefile delete mode 100644 arch/riscv/cpu/nx25/cpu.c delete mode 100644 arch/riscv/cpu/nx25/start.S delete mode 100644 arch/riscv/cpu/nx25/u-boot.lds delete mode 100644 arch/riscv/dts/ae250.dts create mode 100644 arch/riscv/dts/ae350.dts (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c50be37c97..20a43d88e3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,12 +8,12 @@ choice prompt "Target select" optional -config TARGET_NX25_AE250 - bool "Support nx25-ae250" +config TARGET_AX25_AE350 + bool "Support ax25-ae350" endchoice -source "board/AndesTech/nx25-ae250/Kconfig" +source "board/AndesTech/ax25-ae350/Kconfig" choice prompt "CPU selection" diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile new file mode 100644 index 0000000000..c3f164c122 --- /dev/null +++ b/arch/riscv/cpu/ax25/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation + +extra-y = start.o + +obj-y := cpu.o diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c new file mode 100644 index 0000000000..ab05b57d4f --- /dev/null +++ b/arch/riscv/cpu/ax25/cpu.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +/* CPU specific code */ +#include +#include +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + /* turn off I/D-cache */ + + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + disable_interrupts(); + panic("ax25-ae350 wdt not support yet.\n"); +} diff --git a/arch/riscv/cpu/ax25/start.S b/arch/riscv/cpu/ax25/start.S new file mode 100644 index 0000000000..7cd7755190 --- /dev/null +++ b/arch/riscv/cpu/ax25/start.S @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Startup Code for RISC-V Core + * + * Copyright (c) 2017 Microsemi Corporation. + * Copyright (c) 2017 Padmarao Begari + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_32BIT +#define LREG lw +#define SREG sw +#define REGBYTES 4 +#define RELOC_TYPE R_RISCV_32 +#define SYM_INDEX 0x8 +#define SYM_SIZE 0x10 +#else +#define LREG ld +#define SREG sd +#define REGBYTES 8 +#define RELOC_TYPE R_RISCV_64 +#define SYM_INDEX 0x20 +#define SYM_SIZE 0x18 +#endif + +.section .text +.globl _start +_start: + j handle_reset + +nmi_vector: + j nmi_vector + +trap_vector: + j trap_entry + +.global trap_entry +handle_reset: + li t0, CONFIG_SYS_SDRAM_BASE + SREG a2, 0(t0) + la t0, trap_entry + csrw mtvec, t0 + csrwi mstatus, 0 + csrwi mie, 0 + +/* + * Do CPU critical regs init only at reboot, + * not when booting from ram + */ +#ifdef CONFIG_INIT_CRITICAL + jal cpu_init_crit /* Do CPU critical regs init */ +#endif + +/* + * Set stackpointer in internal/ex RAM to call board_init_f + */ +call_board_init_f: + li t0, -16 + li t1, CONFIG_SYS_INIT_SP_ADDR + and sp, t1, t0 /* force 16 byte alignment */ + +#ifdef CONFIG_DEBUG_UART + jal debug_uart_init +#endif + +call_board_init_f_0: + mv a0, sp + jal board_init_f_alloc_reserve + mv sp, a0 + jal board_init_f_init_reserve + + mv a0, zero /* a0 <-- boot_flags = 0 */ + la t5, board_init_f + jr t5 /* jump to board_init_f() */ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ +.globl relocate_code +relocate_code: + mv s2, a0 /* save addr_sp */ + mv s3, a1 /* save addr of gd */ + mv s4, a2 /* save addr of destination */ + +/* + *Set up the stack + */ +stack_setup: + mv sp, s2 + la t0, _start + sub t6, s4, t0 /* t6 <- relocation offset */ + beq t0, s4, clear_bss /* skip relocation */ + + mv t1, s4 /* t1 <- scratch for copy_loop */ + la t3, __bss_start + sub t3, t3, t0 /* t3 <- __bss_start_ofs */ + add t2, t0, t3 /* t2 <- source end address */ + +copy_loop: + LREG t5, 0(t0) + addi t0, t0, REGBYTES + SREG t5, 0(t1) + addi t1, t1, REGBYTES + blt t0, t2, copy_loop + +/* + * Update dynamic relocations after board_init_f + */ +fix_rela_dyn: + la t1, __rel_dyn_start + la t2, __rel_dyn_end + beq t1, t2, clear_bss + add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ + add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ + +/* + * skip first reserved entry: address, type, addend + */ + bne t1, t2, 7f + +6: + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ + bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ + LREG t3, -(REGBYTES*3)(t1) + LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) +7: + addi t1, t1, (REGBYTES*3) + ble t1, t2, 6b + +8: + la t4, __dyn_sym_start + add t4, t4, t6 + +9: + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ + andi t5, t5, 0xFF /* t5 <--- relocation type */ + li t3, RELOC_TYPE + bne t5, t3, 10f /* skip non-addned entries */ + + LREG t3, -(REGBYTES*3)(t1) + li t5, SYM_SIZE + mul t0, t0, t5 + add s1, t4, t0 + LREG t5, REGBYTES(s1) + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) +10: + addi t1, t1, (REGBYTES*3) + ble t1, t2, 9b + +/* + * trap update +*/ + la t0, trap_entry + add t0, t0, t6 + csrw mtvec, t0 + +clear_bss: + la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ + add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ + la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ + add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ + li t2, 0x00000000 /* clear */ + beq t0, t1, call_board_init_r + +clbss_l: + SREG t2, 0(t0) /* clear loop... */ + addi t0, t0, REGBYTES + bne t0, t1, clbss_l + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +call_board_init_r: + la t0, board_init_r + mv t4, t0 /* offset of board_init_r() */ + add t4, t4, t6 /* real address of board_init_r() */ +/* + * setup parameters for board_init_r + */ + mv a0, s3 /* gd_t */ + mv a1, s4 /* dest_addr */ + +/* + * jump to it ... + */ + jr t4 /* jump to board_init_r() */ + +/* + * trap entry + */ +trap_entry: + addi sp, sp, -32*REGBYTES + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + SREG x16, 16*REGBYTES(sp) + SREG x17, 17*REGBYTES(sp) + SREG x18, 18*REGBYTES(sp) + SREG x19, 19*REGBYTES(sp) + SREG x20, 20*REGBYTES(sp) + SREG x21, 21*REGBYTES(sp) + SREG x22, 22*REGBYTES(sp) + SREG x23, 23*REGBYTES(sp) + SREG x24, 24*REGBYTES(sp) + SREG x25, 25*REGBYTES(sp) + SREG x26, 26*REGBYTES(sp) + SREG x27, 27*REGBYTES(sp) + SREG x28, 28*REGBYTES(sp) + SREG x29, 29*REGBYTES(sp) + SREG x30, 30*REGBYTES(sp) + SREG x31, 31*REGBYTES(sp) + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + +/* + * Remain in M-mode after mret + */ + li t0, MSTATUS_MPP + csrs mstatus, t0 + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + LREG x16, 16*REGBYTES(sp) + LREG x17, 17*REGBYTES(sp) + LREG x18, 18*REGBYTES(sp) + LREG x19, 19*REGBYTES(sp) + LREG x20, 20*REGBYTES(sp) + LREG x21, 21*REGBYTES(sp) + LREG x22, 22*REGBYTES(sp) + LREG x23, 23*REGBYTES(sp) + LREG x24, 24*REGBYTES(sp) + LREG x25, 25*REGBYTES(sp) + LREG x26, 26*REGBYTES(sp) + LREG x27, 27*REGBYTES(sp) + LREG x28, 28*REGBYTES(sp) + LREG x29, 29*REGBYTES(sp) + LREG x30, 30*REGBYTES(sp) + LREG x31, 31*REGBYTES(sp) + addi sp, sp, 32*REGBYTES + mret + +#ifdef CONFIG_INIT_CRITICAL +cpu_init_crit: + ret +#endif diff --git a/arch/riscv/cpu/ax25/u-boot.lds b/arch/riscv/cpu/ax25/u-boot.lds new file mode 100644 index 0000000000..1589babf6c --- /dev/null +++ b/arch/riscv/cpu/ax25/u-boot.lds @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ +OUTPUT_ARCH("riscv") +ENTRY(_start) + +SECTIONS +{ + . = ALIGN(4); + .text : + { + arch/riscv/cpu/ax25/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + __global_pointer$ = . + 0x800; + *(.data*) + } + . = ALIGN(4); + + .got : { + __got_start = .; + *(.got.plt) *(.got) + __got_end = .; + } + + . = ALIGN(4); + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .efi_runtime : { + __efi_runtime_start = .; + *(efi_runtime_text) + *(efi_runtime_data) + __efi_runtime_stop = .; + } + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.relaefi_runtime_text) + *(.relaefi_runtime_data) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(4); + + /DISCARD/ : { *(.rela.plt*) } + .rela.dyn : { + __rel_dyn_start = .; + *(.rela*) + __rel_dyn_end = .; + } + + . = ALIGN(4); + + .dynsym : { + __dyn_sym_start = .; + *(.dynsym) + __dyn_sym_end = .; + } + + . = ALIGN(4); + + _end = .; + + .bss : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end = .; + } + +} diff --git a/arch/riscv/cpu/nx25/Makefile b/arch/riscv/cpu/nx25/Makefile deleted file mode 100644 index c3f164c122..0000000000 --- a/arch/riscv/cpu/nx25/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2017 Andes Technology Corporation -# Rick Chen, Andes Technology Corporation - -extra-y = start.o - -obj-y := cpu.o diff --git a/arch/riscv/cpu/nx25/cpu.c b/arch/riscv/cpu/nx25/cpu.c deleted file mode 100644 index 091e9ef59e..0000000000 --- a/arch/riscv/cpu/nx25/cpu.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -/* CPU specific code */ -#include -#include -#include -#include - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - /* turn off I/D-cache */ - - return 0; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - disable_interrupts(); - panic("nx25-ae250 wdt not support yet.\n"); -} diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S deleted file mode 100644 index 7cd7755190..0000000000 --- a/arch/riscv/cpu/nx25/start.S +++ /dev/null @@ -1,292 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Startup Code for RISC-V Core - * - * Copyright (c) 2017 Microsemi Corporation. - * Copyright (c) 2017 Padmarao Begari - * - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_32BIT -#define LREG lw -#define SREG sw -#define REGBYTES 4 -#define RELOC_TYPE R_RISCV_32 -#define SYM_INDEX 0x8 -#define SYM_SIZE 0x10 -#else -#define LREG ld -#define SREG sd -#define REGBYTES 8 -#define RELOC_TYPE R_RISCV_64 -#define SYM_INDEX 0x20 -#define SYM_SIZE 0x18 -#endif - -.section .text -.globl _start -_start: - j handle_reset - -nmi_vector: - j nmi_vector - -trap_vector: - j trap_entry - -.global trap_entry -handle_reset: - li t0, CONFIG_SYS_SDRAM_BASE - SREG a2, 0(t0) - la t0, trap_entry - csrw mtvec, t0 - csrwi mstatus, 0 - csrwi mie, 0 - -/* - * Do CPU critical regs init only at reboot, - * not when booting from ram - */ -#ifdef CONFIG_INIT_CRITICAL - jal cpu_init_crit /* Do CPU critical regs init */ -#endif - -/* - * Set stackpointer in internal/ex RAM to call board_init_f - */ -call_board_init_f: - li t0, -16 - li t1, CONFIG_SYS_INIT_SP_ADDR - and sp, t1, t0 /* force 16 byte alignment */ - -#ifdef CONFIG_DEBUG_UART - jal debug_uart_init -#endif - -call_board_init_f_0: - mv a0, sp - jal board_init_f_alloc_reserve - mv sp, a0 - jal board_init_f_init_reserve - - mv a0, zero /* a0 <-- boot_flags = 0 */ - la t5, board_init_f - jr t5 /* jump to board_init_f() */ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - */ -.globl relocate_code -relocate_code: - mv s2, a0 /* save addr_sp */ - mv s3, a1 /* save addr of gd */ - mv s4, a2 /* save addr of destination */ - -/* - *Set up the stack - */ -stack_setup: - mv sp, s2 - la t0, _start - sub t6, s4, t0 /* t6 <- relocation offset */ - beq t0, s4, clear_bss /* skip relocation */ - - mv t1, s4 /* t1 <- scratch for copy_loop */ - la t3, __bss_start - sub t3, t3, t0 /* t3 <- __bss_start_ofs */ - add t2, t0, t3 /* t2 <- source end address */ - -copy_loop: - LREG t5, 0(t0) - addi t0, t0, REGBYTES - SREG t5, 0(t1) - addi t1, t1, REGBYTES - blt t0, t2, copy_loop - -/* - * Update dynamic relocations after board_init_f - */ -fix_rela_dyn: - la t1, __rel_dyn_start - la t2, __rel_dyn_end - beq t1, t2, clear_bss - add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ - add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ - -/* - * skip first reserved entry: address, type, addend - */ - bne t1, t2, 7f - -6: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ - li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ - bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ - LREG t3, -(REGBYTES*3)(t1) - LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ - add t5, t5, t6 /* t5 <-- location to fix up in RAM */ - add t3, t3, t6 /* t3 <-- location to fix up in RAM */ - SREG t5, 0(t3) -7: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 6b - -8: - la t4, __dyn_sym_start - add t4, t4, t6 - -9: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ - srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ - andi t5, t5, 0xFF /* t5 <--- relocation type */ - li t3, RELOC_TYPE - bne t5, t3, 10f /* skip non-addned entries */ - - LREG t3, -(REGBYTES*3)(t1) - li t5, SYM_SIZE - mul t0, t0, t5 - add s1, t4, t0 - LREG t5, REGBYTES(s1) - add t5, t5, t6 /* t5 <-- location to fix up in RAM */ - add t3, t3, t6 /* t3 <-- location to fix up in RAM */ - SREG t5, 0(t3) -10: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 9b - -/* - * trap update -*/ - la t0, trap_entry - add t0, t0, t6 - csrw mtvec, t0 - -clear_bss: - la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ - add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ - la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ - add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ - li t2, 0x00000000 /* clear */ - beq t0, t1, call_board_init_r - -clbss_l: - SREG t2, 0(t0) /* clear loop... */ - addi t0, t0, REGBYTES - bne t0, t1, clbss_l - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -call_board_init_r: - la t0, board_init_r - mv t4, t0 /* offset of board_init_r() */ - add t4, t4, t6 /* real address of board_init_r() */ -/* - * setup parameters for board_init_r - */ - mv a0, s3 /* gd_t */ - mv a1, s4 /* dest_addr */ - -/* - * jump to it ... - */ - jr t4 /* jump to board_init_r() */ - -/* - * trap entry - */ -trap_entry: - addi sp, sp, -32*REGBYTES - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - csrw mepc, a0 - -/* - * Remain in M-mode after mret - */ - li t0, MSTATUS_MPP - csrs mstatus, t0 - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) - addi sp, sp, 32*REGBYTES - mret - -#ifdef CONFIG_INIT_CRITICAL -cpu_init_crit: - ret -#endif diff --git a/arch/riscv/cpu/nx25/u-boot.lds b/arch/riscv/cpu/nx25/u-boot.lds deleted file mode 100644 index c53829a07c..0000000000 --- a/arch/riscv/cpu/nx25/u-boot.lds +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ -OUTPUT_ARCH("riscv") -ENTRY(_start) - -SECTIONS -{ - . = ALIGN(4); - .text : - { - arch/riscv/cpu/nx25/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - __global_pointer$ = . + 0x800; - *(.data*) - } - . = ALIGN(4); - - .got : { - __got_start = .; - *(.got.plt) *(.got) - __got_end = .; - } - - . = ALIGN(4); - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .efi_runtime : { - __efi_runtime_start = .; - *(efi_runtime_text) - *(efi_runtime_data) - __efi_runtime_stop = .; - } - - .efi_runtime_rel : { - __efi_runtime_rel_start = .; - *(.relaefi_runtime_text) - *(.relaefi_runtime_data) - __efi_runtime_rel_stop = .; - } - - . = ALIGN(4); - - /DISCARD/ : { *(.rela.plt*) } - .rela.dyn : { - __rel_dyn_start = .; - *(.rela*) - __rel_dyn_end = .; - } - - . = ALIGN(4); - - .dynsym : { - __dyn_sym_start = .; - *(.dynsym) - __dyn_sym_end = .; - } - - . = ALIGN(4); - - _end = .; - - .bss : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end = .; - } - -} diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 793677524a..a1b06ffc6f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_NX25_AE250) += ae250.dtb +dtb-$(CONFIG_TARGET_AX25_AE350) += ae350.dtb targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/riscv/dts/ae250.dts b/arch/riscv/dts/ae250.dts deleted file mode 100644 index 9a38345e36..0000000000 --- a/arch/riscv/dts/ae250.dts +++ /dev/null @@ -1,97 +0,0 @@ -/dts-v1/; -/ { - compatible = "riscv32 nx25"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - aliases { - uart0 = &serial0; - ethernet0 = &mac0; - spi0 = &spi; - } ; - - chosen { - bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; - stdout-path = "uart0:38400n8"; - tick-timer = &timer0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "andestech,n13"; - reg = <0>; - /* FIXME: to fill correct frqeuency */ - clock-frequency = <60000000>; - }; - }; - - intc: interrupt-controller { - compatible = "andestech,atnointc010"; - #interrupt-cells = <1>; - interrupt-controller; - }; - - serial0: serial@f0300000 { - compatible = "andestech,uart16550", "ns16550a"; - reg = <0xf0300000 0x1000>; - interrupts = <7 4>; - clock-frequency = <19660800>; - reg-shift = <2>; - reg-offset = <32>; - no-loopback-test = <1>; - }; - - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0xf0400000 0x1000>; - interrupts = <2 4>; - clock-frequency = <40000000>; - }; - - mac0: mac@e0100000 { - compatible = "andestech,atmac100"; - reg = <0xe0100000 0x1000>; - interrupts = <25 4>; - }; - - mmc0: mmc@f0e00000 { - compatible = "andestech,atsdc010"; - max-frequency = <100000000>; - fifo-depth = <0x10>; - reg = <0xf0e00000 0x1000>; - interrupts = <17 4>; - cap-sd-highspeed; - }; - - spi: spi@f0b00000 { - compatible = "andestech,atcspi200"; - reg = <0xf0b00000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - clocks = <&spiclk>; - interrupts = <3 4>; - flash@0 { - compatible = "spi-flash"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-cpol; - spi-cpha; - }; - }; - -}; diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts new file mode 100644 index 0000000000..9a38345e36 --- /dev/null +++ b/arch/riscv/dts/ae350.dts @@ -0,0 +1,97 @@ +/dts-v1/; +/ { + compatible = "riscv32 nx25"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + ethernet0 = &mac0; + spi0 = &spi; + } ; + + chosen { + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <7 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <40000000>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <25 4>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atsdc010"; + max-frequency = <100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <17 4>; + cap-sd-highspeed; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0xf0b00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <3 4>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; + +}; diff --git a/arch/riscv/include/asm/mach-types.h b/arch/riscv/include/asm/mach-types.h index 93afff70b3..f219cedfd3 100644 --- a/arch/riscv/include/asm/mach-types.h +++ b/arch/riscv/include/asm/mach-types.h @@ -12,18 +12,18 @@ extern unsigned int __machine_arch_type; #endif -#define MACH_TYPE_AE250 1 +#define MACH_TYPE_AE350 1 -#ifdef CONFIG_ARCH_AE250 +#ifdef CONFIG_ARCH_AE350 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_AE250 +# define machine_arch_type MACH_TYPE_AE350 # endif -# define machine_is_ae250() (machine_arch_type == MACH_TYPE_AE250) +# define machine_is_ae350() (machine_arch_type == MACH_TYPE_AE350) #else -# define machine_is_ae250() (1) +# define machine_is_ae350() (1) #endif #endif /* __ASM_RISCV_MACH_TYPE_H */ -- cgit v1.2.3 From c14e90e8445e7b1c3531b4bdeb778c47bd6570eb Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 29 May 2018 10:53:41 +0800 Subject: riscv: dts: Sync DT with Linux Kernel Use same dts to boot U-Boot and RISC-V Linux Kernel v4.16-rc2 in ax25-ae350 platform. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts | 116 +++++++++++++++++++++++++++++++---------------- 1 file changed, 78 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts index 9a38345e36..cf84640fc7 100644 --- a/arch/riscv/dts/ae350.dts +++ b/arch/riscv/dts/ae350.dts @@ -1,90 +1,131 @@ /dts-v1/; + / { - compatible = "riscv32 nx25"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,ax25"; + model = "andestech,ax25"; aliases { uart0 = &serial0; - ethernet0 = &mac0; spi0 = &spi; } ; chosen { bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; stdout-path = "uart0:38400n8"; - tick-timer = &timer0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; memory@0 { device_type = "memory"; - reg = <0x00000000 0x40000000>; + reg = <0x0 0x00000000 0x0 0x40000000>; }; - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,riscv-ae350-soc"; + ranges; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "andestech,n13"; - reg = <0>; - /* FIXME: to fill correct frqeuency */ - clock-frequency = <60000000>; + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0x0 0xe6000000 0x0 0x100000>; }; + + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe4000000 0x0 0x2000000>; + riscv,ndev=<31>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; }; - intc: interrupt-controller { - compatible = "andestech,atnointc010"; - #interrupt-cells = <1>; + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #address-cells = <2>; + #interrupt-cells = <2>; interrupt-controller; + reg = <0x0 0xe6400000 0x0 0x400000>; + riscv,ndev=<1>; + interrupts-extended = <&CPU0_intc 3>; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0x0 0xf0400000 0x0 0x1000>; + clock-frequency = <40000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; }; serial0: serial@f0300000 { compatible = "andestech,uart16550", "ns16550a"; - reg = <0xf0300000 0x1000>; - interrupts = <7 4>; + reg = <0x0 0xf0300000 0x0 0x1000>; + interrupts = <9 4>; clock-frequency = <19660800>; reg-shift = <2>; reg-offset = <32>; no-loopback-test = <1>; - }; - - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0xf0400000 0x1000>; - interrupts = <2 4>; - clock-frequency = <40000000>; + interrupt-parent = <&plic0>; }; mac0: mac@e0100000 { compatible = "andestech,atmac100"; - reg = <0xe0100000 0x1000>; - interrupts = <25 4>; + reg = <0x0 0xe0100000 0x0 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; }; mmc0: mmc@f0e00000 { - compatible = "andestech,atsdc010"; + compatible = "andestech,atfsdc010"; max-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; fifo-depth = <0x10>; - reg = <0xf0e00000 0x1000>; - interrupts = <17 4>; + reg = <0x0 0xf0e00000 0x0 0x1000>; + interrupts = <18 4>; cap-sd-highspeed; + interrupt-parent = <&plic0>; }; spi: spi@f0b00000 { compatible = "andestech,atcspi200"; - reg = <0xf0b00000 0x1000>; + reg = <0x0 0xf0b00000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; clocks = <&spiclk>; interrupts = <3 4>; + interrupt-parent = <&plic0>; flash@0 { compatible = "spi-flash"; spi-max-frequency = <50000000>; @@ -93,5 +134,4 @@ spi-cpha; }; }; - }; -- cgit v1.2.3 From 7286e46a790b0e007b4039b3d415a230d5ab84be Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 29 May 2018 11:05:54 +0800 Subject: riscv: dts: Support cfi flash Add nor node for cfi-flash driver and smc node for smc(aftsmc020) controller. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts index cf84640fc7..2927e4151b 100644 --- a/arch/riscv/dts/ae350.dts +++ b/arch/riscv/dts/ae350.dts @@ -117,6 +117,18 @@ interrupt-parent = <&plic0>; }; + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0x0 0xe0400000 0x0 0x1000>; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x88000000 0x0 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + spi: spi@f0b00000 { compatible = "andestech,atcspi200"; reg = <0x0 0xf0b00000 0x0 0x1000>; -- cgit v1.2.3