From 7f491d7b30a152ad635d46cb795013b447e0a82f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 30 Aug 2016 16:17:27 +0200 Subject: ARM64: zynqmp: Force certain bootmode for SPL ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/Kconfig | 48 +++++++++++++++++++++++++++++ arch/arm/cpu/armv8/zynqmp/spl.c | 7 +++++ arch/arm/include/asm/arch-zynqmp/hardware.h | 2 ++ 3 files changed, 57 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e7039919c70..1eedb39aa5a 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -47,5 +47,53 @@ config ZYNQMP_USB config SYS_MALLOC_F_LEN default 0x600 +config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED + bool "Overwrite SPL bootmode" + depends on SPL + help + Overwrite bootmode selected via boot mode pins to tell SPL what should + be the next boot device. + +config SPL_ZYNQMP_ALT_BOOTMODE + hex + default 0x0 if JTAG_MODE + default 0x1 if QSPI_MODE_24BIT + default 0x2 if QSPI_MODE_32BIT + default 0x3 if SD_MODE + default 0x4 if NAND_MODE + default 0x5 if SD_MODE1 + default 0x6 if EMMC_MODE + default 0x7 if USB_MODE + +choice + prompt "Boot mode" + depends on ZYNQMP_ALT_BOOTMODE_ENABLED + default JTAG + +config JTAG_MODE + bool "JTAG_MODE" + +config QSPI_MODE_24BIT + bool "QSPI_MODE_24BIT" + +config QSPI_MODE_32BIT + bool "QSPI_MODE_32BIT" + +config SD_MODE + bool "SD_MODE" + +config SD_MODE1 + bool "SD_MODE1" + +config NAND_MODE + bool "NAND_MODE" + +config EMMC_MODE + bool "EMMC_MODE" + +config USB_MODE + bool "USB" + +endchoice endif diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 867d2b25a88..4b6fdc25934 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -48,6 +48,13 @@ u32 spl_boot_device(void) u32 reg = 0; u8 bootmode; +#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED) + /* Change default boot mode at run-time */ + writel(BOOT_MODE_USE_ALT | + CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT, + &crlapb_base->boot_mode); +#endif + reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 35964d603b3..bcb243416a2 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -70,6 +70,8 @@ struct iou_scntr_secure { #define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 -- cgit v1.2.3 From 3373a5228337a4a71d02a5184a3425b651eda0ff Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 29 Apr 2016 13:00:10 +0200 Subject: ARM64: zynqmp: Add USB boot mode Add USB boot mode. Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/hardware.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index bcb243416a2..10d67d0fb7b 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -69,6 +69,7 @@ struct iou_scntr_secure { #define SD_MODE1 0x00000005 /* sd 1 */ #define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 -- cgit v1.2.3 From e1024c9808c00bb61cf58e47cac6ff76905bf339 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 30 Aug 2016 15:38:57 +0200 Subject: ARM: Add new BOOT_DEVICE_DFU boot mode This enum is needed when SPL_DFU is enabled. Signed-off-by: Michal Simek --- arch/arm/include/asm/spl.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 19c38f4083c..6f312d6652a 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -28,6 +28,7 @@ enum { BOOT_DEVICE_SATA, BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, + BOOT_DEVICE_DFU, BOOT_DEVICE_NONE }; #endif -- cgit v1.2.3 From d58fc12eb7f40a208e22b57037436411ea36125c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 19 Aug 2016 14:14:52 +0200 Subject: ARM64: zynqmp: Add support for DFU from SPL SPL needs to have bigger stack size because of USB. Simple malloc needs to be disabled because dfu code requires different allocation functions. There is no space in OCM that's why random place in DDR is used. BOOTD must be disabled because it is causing compilation error. All variables are disabled and used only variables valid for DFU because they are simple huge. Including automatic variables added by CONFIG_ENV_VARS_UBOOT_CONFIG. Hardcode addresses for u-boot, atf, kernel and dtb just for SPL DFU code. Enable SPL DFU for zcu100. Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/spl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 4b6fdc25934..3ad5de14087 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -66,6 +66,10 @@ u32 spl_boot_device(void) case SD_MODE: case SD_MODE1: return BOOT_DEVICE_MMC1; +#endif +#ifdef CONFIG_SPL_DFU_SUPPORT + case USB_MODE: + return BOOT_DEVICE_DFU; #endif default: printf("Invalid Boot Mode:0x%x\n", bootmode); -- cgit v1.2.3 From 48255f52764b64f35a268e4e87f2c3a621741836 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 15 Aug 2016 09:41:36 +0200 Subject: ARM64: zynqmp: Add support for USB ulpi phy reset via mode pins Mode pins can be used as output for reset. Xilinx boards are using this feature as additional way how to reset USB phys and also others chips on the boards. Mode1 is used on all these boards for this feature. Let SPL toggle reset on this pin by default. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/spl.c | 23 +++++++++++++++++++++++ arch/arm/include/asm/arch-zynqmp/hardware.h | 11 ++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 3ad5de14087..552f577b95d 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -35,10 +35,33 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +static void ps_mode_reset(ulong mode) +{ + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | + mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); + udelay(1); + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); + udelay(5); + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | + mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); +} + +/* + * Set default PS_MODE1 which is used for USB ULPI phy reset + * Also other resets can be connected to this certain pin + */ +#ifndef MODE_RESET +# define MODE_RESET PS_MODE1 +#endif + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void) { preloader_console_init(); + ps_mode_reset(MODE_RESET); board_init(); } #endif diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 10d67d0fb7b..456c1b0902e 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -25,6 +25,13 @@ #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 + +#define PS_MODE0 BIT(0) +#define PS_MODE1 BIT(1) +#define PS_MODE2 BIT(2) +#define PS_MODE3 BIT(3) struct crlapb_regs { u32 reserved0[36]; @@ -35,7 +42,9 @@ struct crlapb_regs { u32 boot_mode; /* 0x200 */ u32 reserved3[14]; u32 rst_lpd_top; /* 0x23C */ - u32 reserved4[26]; + u32 reserved4[4]; + u32 boot_pin_ctrl; /* 0x250 */ + u32 reserved5[21]; }; #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) -- cgit v1.2.3 From 5242772c5113850c0c35d6271fd281dfc669c707 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 16 Aug 2016 15:40:05 +0200 Subject: ARM64: zynqmp: Fix USB ulpi phy sequence It should be enough to call low(5us)->high pulse for all cases to provide proper reset. There is no need to call high->low->high. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/spl.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 552f577b95d..04e190537d1 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -37,10 +37,6 @@ void board_init_f(ulong dummy) static void ps_mode_reset(ulong mode) { - writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | - mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, - &crlapb_base->boot_pin_ctrl); - udelay(1); writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, &crlapb_base->boot_pin_ctrl); udelay(5); -- cgit v1.2.3