From 5d73bc7af75b004d4eb343572e3ff5bc5727a048 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Thu, 4 Nov 2010 23:15:30 +0000 Subject: avr32: rename memory-map.h -> hardware.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- arch/avr32/cpu/at32ap700x/clk.c | 2 +- arch/avr32/cpu/at32ap700x/portmux.c | 2 +- arch/avr32/cpu/cpu.c | 2 +- arch/avr32/cpu/hsdramc.c | 2 +- arch/avr32/cpu/interrupts.c | 2 +- arch/avr32/cpu/portmux-gpio.c | 2 +- arch/avr32/cpu/portmux-pio.c | 2 +- arch/avr32/include/asm/arch-at32ap700x/gpio.h | 2 +- arch/avr32/include/asm/arch-at32ap700x/hardware.h | 86 ++++++++++++++++++++++ .../avr32/include/asm/arch-at32ap700x/memory-map.h | 86 ---------------------- 10 files changed, 94 insertions(+), 94 deletions(-) create mode 100644 arch/avr32/include/asm/arch-at32ap700x/hardware.h delete mode 100644 arch/avr32/include/asm/arch-at32ap700x/memory-map.h (limited to 'arch') diff --git a/arch/avr32/cpu/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c index 742bc6b5a2..b63b9df143 100644 --- a/arch/avr32/cpu/at32ap700x/clk.c +++ b/arch/avr32/cpu/at32ap700x/clk.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include #include "sm.h" diff --git a/arch/avr32/cpu/at32ap700x/portmux.c b/arch/avr32/cpu/at32ap700x/portmux.c index b1f2c6f1ff..e3e38a2a75 100644 --- a/arch/avr32/cpu/at32ap700x/portmux.c +++ b/arch/avr32/cpu/at32ap700x/portmux.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include /* diff --git a/arch/avr32/cpu/cpu.c b/arch/avr32/cpu/cpu.c index e4489bb2e2..790783767f 100644 --- a/arch/avr32/cpu/cpu.c +++ b/arch/avr32/cpu/cpu.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include "hsmc3.h" diff --git a/arch/avr32/cpu/hsdramc.c b/arch/avr32/cpu/hsdramc.c index b6eae667c2..1485494f49 100644 --- a/arch/avr32/cpu/hsdramc.c +++ b/arch/avr32/cpu/hsdramc.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include "hsdramc1.h" diff --git a/arch/avr32/cpu/interrupts.c b/arch/avr32/cpu/interrupts.c index c6d8d16e39..c751981b34 100644 --- a/arch/avr32/cpu/interrupts.c +++ b/arch/avr32/cpu/interrupts.c @@ -27,7 +27,7 @@ #include #include -#include +#include #define HANDLER_MASK 0x00ffffff #define INTLEV_SHIFT 30 diff --git a/arch/avr32/cpu/portmux-gpio.c b/arch/avr32/cpu/portmux-gpio.c index 9acd040d1b..7b64c89a98 100644 --- a/arch/avr32/cpu/portmux-gpio.c +++ b/arch/avr32/cpu/portmux-gpio.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include void portmux_select_peripheral(void *port, unsigned long pin_mask, diff --git a/arch/avr32/cpu/portmux-pio.c b/arch/avr32/cpu/portmux-pio.c index a29f94e3ba..cb5e96205a 100644 --- a/arch/avr32/cpu/portmux-pio.c +++ b/arch/avr32/cpu/portmux-pio.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include void portmux_select_peripheral(void *port, unsigned long pin_mask, diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio.h b/arch/avr32/include/asm/arch-at32ap700x/gpio.h index 303e35313a..b0254f2d7f 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/gpio.h +++ b/arch/avr32/include/asm/arch-at32ap700x/gpio.h @@ -23,7 +23,7 @@ #define __ASM_AVR32_ARCH_GPIO_H__ #include -#include +#include #define NR_GPIO_CONTROLLERS 5 diff --git a/arch/avr32/include/asm/arch-at32ap700x/hardware.h b/arch/avr32/include/asm/arch-at32ap700x/hardware.h new file mode 100644 index 0000000000..6592c039fa --- /dev/null +++ b/arch/avr32/include/asm/arch-at32ap700x/hardware.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __AT32AP7000_MEMORY_MAP_H__ +#define __AT32AP7000_MEMORY_MAP_H__ + +/* Internal and external memories */ +#define EBI_SRAM_CS0_BASE 0x00000000 +#define EBI_SRAM_CS0_SIZE 0x04000000 +#define EBI_SRAM_CS4_BASE 0x04000000 +#define EBI_SRAM_CS4_SIZE 0x04000000 +#define EBI_SRAM_CS2_BASE 0x08000000 +#define EBI_SRAM_CS2_SIZE 0x04000000 +#define EBI_SRAM_CS3_BASE 0x0c000000 +#define EBI_SRAM_CS3_SIZE 0x04000000 +#define EBI_SRAM_CS1_BASE 0x10000000 +#define EBI_SRAM_CS1_SIZE 0x10000000 +#define EBI_SRAM_CS5_BASE 0x20000000 +#define EBI_SRAM_CS5_SIZE 0x04000000 + +#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE +#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE + +#define INTERNAL_SRAM_BASE 0x24000000 +#define INTERNAL_SRAM_SIZE 0x00008000 + +/* Devices on the High Speed Bus (HSB) */ +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 + +/* Devices on Peripheral Bus A (PBA) */ +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 + +/* Devices on Peripheral Bus B (PBB) */ +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0xFFF00400 +#define HMATRIX_BASE 0xFFF00800 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define PWM_BASE 0xFFF01400 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define DAC_BASE 0xFFF02000 +#define MMCI_BASE 0xFFF02400 +#define AUDIOC_BASE 0xFFF02800 +#define HISI_BASE 0xFFF02C00 +#define USB_BASE 0xFFF03000 +#define HSMC_BASE 0xFFF03400 +#define HSDRAMC_BASE 0xFFF03800 +#define ECC_BASE 0xFFF03C00 + +#endif /* __AT32AP7000_MEMORY_MAP_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/memory-map.h b/arch/avr32/include/asm/arch-at32ap700x/memory-map.h deleted file mode 100644 index 6592c039fa..0000000000 --- a/arch/avr32/include/asm/arch-at32ap700x/memory-map.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __AT32AP7000_MEMORY_MAP_H__ -#define __AT32AP7000_MEMORY_MAP_H__ - -/* Internal and external memories */ -#define EBI_SRAM_CS0_BASE 0x00000000 -#define EBI_SRAM_CS0_SIZE 0x04000000 -#define EBI_SRAM_CS4_BASE 0x04000000 -#define EBI_SRAM_CS4_SIZE 0x04000000 -#define EBI_SRAM_CS2_BASE 0x08000000 -#define EBI_SRAM_CS2_SIZE 0x04000000 -#define EBI_SRAM_CS3_BASE 0x0c000000 -#define EBI_SRAM_CS3_SIZE 0x04000000 -#define EBI_SRAM_CS1_BASE 0x10000000 -#define EBI_SRAM_CS1_SIZE 0x10000000 -#define EBI_SRAM_CS5_BASE 0x20000000 -#define EBI_SRAM_CS5_SIZE 0x04000000 - -#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE -#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE - -#define INTERNAL_SRAM_BASE 0x24000000 -#define INTERNAL_SRAM_SIZE 0x00008000 - -/* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 - -/* Devices on Peripheral Bus A (PBA) */ -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 - -/* Devices on Peripheral Bus B (PBB) */ -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0xFFF00400 -#define HMATRIX_BASE 0xFFF00800 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define PWM_BASE 0xFFF01400 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define DAC_BASE 0xFFF02000 -#define MMCI_BASE 0xFFF02400 -#define AUDIOC_BASE 0xFFF02800 -#define HISI_BASE 0xFFF02C00 -#define USB_BASE 0xFFF03000 -#define HSMC_BASE 0xFFF03400 -#define HSDRAMC_BASE 0xFFF03800 -#define ECC_BASE 0xFFF03C00 - -#endif /* __AT32AP7000_MEMORY_MAP_H__ */ -- cgit v1.2.3 From f4278b716c2925b4dcf18b94f0ff932d4736cd5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Thu, 4 Nov 2010 23:15:31 +0000 Subject: avr32: fixup definitions to ATMEL_BASE_xxx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- arch/avr32/cpu/at32ap700x/sm.h | 4 +- arch/avr32/cpu/hsdramc1.h | 4 +- arch/avr32/cpu/hsmc3.h | 4 +- arch/avr32/cpu/interrupts.c | 2 +- arch/avr32/include/asm/arch-at32ap700x/gpio.h | 10 +-- arch/avr32/include/asm/arch-at32ap700x/hardware.h | 76 +++++++++++------------ arch/avr32/include/asm/arch-at32ap700x/portmux.h | 10 +-- arch/avr32/include/asm/hmatrix-common.h | 2 +- 8 files changed, 56 insertions(+), 56 deletions(-) (limited to 'arch') diff --git a/arch/avr32/cpu/at32ap700x/sm.h b/arch/avr32/cpu/at32ap700x/sm.h index b6e4409b22..9a3804efe4 100644 --- a/arch/avr32/cpu/at32ap700x/sm.h +++ b/arch/avr32/cpu/at32ap700x/sm.h @@ -197,8 +197,8 @@ /* Register access macros */ #define sm_readl(reg) \ - readl((void *)SM_BASE + SM_##reg) + readl((void *)ATMEL_BASE_SM + SM_##reg) #define sm_writel(reg,value) \ - writel((value), (void *)SM_BASE + SM_##reg) + writel((value), (void *)ATMEL_BASE_SM + SM_##reg) #endif /* __CPU_AT32AP_SM_H__ */ diff --git a/arch/avr32/cpu/hsdramc1.h b/arch/avr32/cpu/hsdramc1.h index 305d2cb5d3..e18e074a7a 100644 --- a/arch/avr32/cpu/hsdramc1.h +++ b/arch/avr32/cpu/hsdramc1.h @@ -136,8 +136,8 @@ /* Register access macros */ #define hsdramc1_readl(reg) \ - readl((void *)HSDRAMC_BASE + HSDRAMC1_##reg) + readl((void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) #define hsdramc1_writel(reg,value) \ - writel((value), (void *)HSDRAMC_BASE + HSDRAMC1_##reg) + writel((value), (void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) #endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff --git a/arch/avr32/cpu/hsmc3.h b/arch/avr32/cpu/hsmc3.h index ca533b922e..ac472952a2 100644 --- a/arch/avr32/cpu/hsmc3.h +++ b/arch/avr32/cpu/hsmc3.h @@ -119,8 +119,8 @@ /* Register access macros */ #define hsmc3_readl(reg) \ - readl((void *)HSMC_BASE + HSMC3_##reg) + readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg) #define hsmc3_writel(reg,value) \ - writel((value), (void *)HSMC_BASE + HSMC3_##reg) + writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg) #endif /* __CPU_AT32AP_HSMC3_H__ */ diff --git a/arch/avr32/cpu/interrupts.c b/arch/avr32/cpu/interrupts.c index c751981b34..c6ea435c1d 100644 --- a/arch/avr32/cpu/interrupts.c +++ b/arch/avr32/cpu/interrupts.c @@ -125,7 +125,7 @@ static int set_interrupt_handler(unsigned int nr, void (*handler)(void), intpr = (handler_addr & HANDLER_MASK); intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT; - writel(intpr, (void *)INTC_BASE + 4 * nr); + writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr); return 0; } diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio.h b/arch/avr32/include/asm/arch-at32ap700x/gpio.h index b0254f2d7f..4322eac1c7 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/gpio.h +++ b/arch/avr32/include/asm/arch-at32ap700x/gpio.h @@ -45,15 +45,15 @@ static inline void *pio_pin_to_port(unsigned int pin) { switch (pin >> 5) { case 0: - return (void *)PIOA_BASE; + return (void *)ATMEL_BASE_PIOA; case 1: - return (void *)PIOB_BASE; + return (void *)ATMEL_BASE_PIOB; case 2: - return (void *)PIOC_BASE; + return (void *)ATMEL_BASE_PIOC; case 3: - return (void *)PIOD_BASE; + return (void *)ATMEL_BASE_PIOD; case 4: - return (void *)PIOE_BASE; + return (void *)ATMEL_BASE_PIOE; default: return NULL; } diff --git a/arch/avr32/include/asm/arch-at32ap700x/hardware.h b/arch/avr32/include/asm/arch-at32ap700x/hardware.h index 6592c039fa..9172eef60f 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/hardware.h +++ b/arch/avr32/include/asm/arch-at32ap700x/hardware.h @@ -19,8 +19,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __AT32AP7000_MEMORY_MAP_H__ -#define __AT32AP7000_MEMORY_MAP_H__ +#ifndef __AT32AP7000_HARDWARE_H__ +#define __AT32AP7000_HARDWARE_H__ /* Internal and external memories */ #define EBI_SRAM_CS0_BASE 0x00000000 @@ -43,44 +43,44 @@ #define INTERNAL_SRAM_SIZE 0x00008000 /* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 /* Devices on Peripheral Bus A (PBA) */ -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 +#define ATMEL_BASE_SPI0 0xFFE00000 +#define ATMEL_BASE_SPI1 0xFFE00400 +#define ATMEL_BASE_TWI0 0xFFE00800 +#define ATMEL_BASE_USART0 0xFFE00C00 +#define ATMEL_BASE_USART1 0xFFE01000 +#define ATMEL_BASE_USART2 0xFFE01400 +#define ATMEL_BASE_USART3 0xFFE01800 +#define ATMEL_BASE_SSC0 0xFFE01C00 +#define ATMEL_BASE_SSC1 0xFFE02000 +#define ATMEL_BASE_SSC2 0xFFE02400 +#define ATMEL_BASE_PIOA 0xFFE02800 +#define ATMEL_BASE_PIOB 0xFFE02C00 +#define ATMEL_BASE_PIOC 0xFFE03000 +#define ATMEL_BASE_PIOD 0xFFE03400 +#define ATMEL_BASE_PIOE 0xFFE03800 +#define ATMEL_BASE_PSIF 0xFFE03C00 /* Devices on Peripheral Bus B (PBB) */ -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0xFFF00400 -#define HMATRIX_BASE 0xFFF00800 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define PWM_BASE 0xFFF01400 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define DAC_BASE 0xFFF02000 -#define MMCI_BASE 0xFFF02400 -#define AUDIOC_BASE 0xFFF02800 -#define HISI_BASE 0xFFF02C00 -#define USB_BASE 0xFFF03000 -#define HSMC_BASE 0xFFF03400 -#define HSDRAMC_BASE 0xFFF03800 -#define ECC_BASE 0xFFF03C00 +#define ATMEL_BASE_SM 0xFFF00000 +#define ATMEL_BASE_INTC 0xFFF00400 +#define ATMEL_BASE_HMATRIX 0xFFF00800 +#define ATMEL_BASE_TIMER0 0xFFF00C00 +#define ATMEL_BASE_TIMER1 0xFFF01000 +#define ATMEL_BASE_PWM 0xFFF01400 +#define ATMEL_BASE_MACB0 0xFFF01800 +#define ATMEL_BASE_MACB1 0xFFF01C00 +#define ATMEL_BASE_DAC 0xFFF02000 +#define ATMEL_BASE_MMCI 0xFFF02400 +#define ATMEL_BASE_AUDIOC 0xFFF02800 +#define ATMEL_BASE_HISI 0xFFF02C00 +#define ATMEL_BASE_USB 0xFFF03000 +#define ATMEL_BASE_HSMC 0xFFF03400 +#define ATMEL_BASE_HSDRAMC 0xFFF03800 +#define ATMEL_BASE_ECC 0xFFF03C00 -#endif /* __AT32AP7000_MEMORY_MAP_H__ */ +#endif /* __AT32AP7000_HARDWARE_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/portmux.h b/arch/avr32/include/asm/arch-at32ap700x/portmux.h index 1ba52e5ddb..859c121aa0 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/portmux.h +++ b/arch/avr32/include/asm/arch-at32ap700x/portmux.h @@ -24,11 +24,11 @@ #include -#define PORTMUX_PORT_A ((void *)PIOA_BASE) -#define PORTMUX_PORT_B ((void *)PIOB_BASE) -#define PORTMUX_PORT_C ((void *)PIOC_BASE) -#define PORTMUX_PORT_D ((void *)PIOD_BASE) -#define PORTMUX_PORT_E ((void *)PIOE_BASE) +#define PORTMUX_PORT_A ((void *)ATMEL_BASE_PIOA) +#define PORTMUX_PORT_B ((void *)ATMEL_BASE_PIOB) +#define PORTMUX_PORT_C ((void *)ATMEL_BASE_PIOC) +#define PORTMUX_PORT_D ((void *)ATMEL_BASE_PIOD) +#define PORTMUX_PORT_E ((void *)ATMEL_BASE_PIOE) void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, unsigned long flags, unsigned long drive_strength); diff --git a/arch/avr32/include/asm/hmatrix-common.h b/arch/avr32/include/asm/hmatrix-common.h index 4b7e6105dd..9a86fe4baa 100644 --- a/arch/avr32/include/asm/hmatrix-common.h +++ b/arch/avr32/include/asm/hmatrix-common.h @@ -117,7 +117,7 @@ struct hmatrix_regs { /* Register access macros */ #define __hmatrix_reg(reg) \ - (((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg) + (((volatile struct hmatrix_regs *)ATMEL_BASE_HMATRIX)->reg) #define hmatrix_read(reg) \ (__hmatrix_reg(reg)) #define hmatrix_write(reg, value) \ -- cgit v1.2.3 From aa0f5ef20d975ba6a8f230d6b023c8954520a5eb Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Tue, 2 Nov 2010 11:55:42 +0100 Subject: AT91: rework at91sam9260.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91sam9260.h | 252 ++++++++++++++------------- 1 file changed, 132 insertions(+), 120 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index 7fd60b74ff..dd68485c62 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -2,9 +2,15 @@ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] * * (C) 2006 Andrew Victor + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). + * Definitions for the SoCs: + * AT91SAM9260, AT91SAM9G20, AT91SAM9XE + * + * Note that those SoCs are mostly software and pin compatible, + * therefore this file applies to all of them. Differences between + * those SoCs are concentrated at the end of this file. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,145 +22,151 @@ #define AT91SAM9260_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ -#define AT91_EMAC_BASE 0xfffc4000 -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_SHDWN_BASE 0xfffffd10 -#define AT91_RTT_BASE 0xfffffd20 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 /* - * The AT91SAM9XE has the GPBRs at a different address than - * the AT91SAM9260/9G20. + * Peripheral identifiers/interrupts. */ -#ifdef CONFIG_AT91SAM9XE -# define AT91_GPR_BASE 0xfffffd60 -#else -# define AT91_GPR_BASE 0xfffffd50 -#endif - -#ifdef CONFIG_AT91_LEGACY +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ +#define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_USART2 8 /* USART 2 */ +#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ +#define ATMEL_ID_UDP 10 /* USB Device Port */ +#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ +#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +/* Reserved: 15 */ +/* Reserved: 16 */ +#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ +#define ATMEL_ID_UHP 20 /* USB Host port */ +#define ATMEL_ID_EMAC0 21 /* Ethernet 0 */ +#define ATMEL_ID_ISI 22 /* Image Sensor Interface */ +#define ATMEL_ID_USART3 23 /* USART 3 */ +#define ATMEL_ID_USART4 24 /* USART 4 */ +/* USART5 or TWI1: 25 */ +#define ATMEL_ID_TC3 26 /* Timer Counter 3 */ +#define ATMEL_ID_TC4 27 /* Timer Counter 4 */ +#define ATMEL_ID_TC5 28 /* Timer Counter 5 */ +#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ /* - * User Peripheral physical base addresses. + * User Peripherals physical base addresses. */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 +#define ATMEL_BASE_TCB0 0xfffa0000 +#define ATMEL_BASE_TC0 0xfffa0000 +#define ATMEL_BASE_TC1 0xfffa0040 +#define ATMEL_BASE_TC2 0xfffa0080 +#define ATMEL_BASE_UDP0 0xfffa4000 +#define ATMEL_BASE_MCI 0xfffa8000 +#define ATMEL_BASE_TWI0 0xfffac000 +#define ATMEL_BASE_USART0 0xfffb0000 +#define ATMEL_BASE_USART1 0xfffb4000 +#define ATMEL_BASE_USART2 0xfffb8000 +#define ATMEL_BASE_SSC0 0xfffbc000 +#define ATMEL_BASE_ISI0 0xfffc0000 +#define ATMEL_BASE_EMAC0 0xfffc4000 +#define ATMEL_BASE_SPI0 0xfffc8000 +#define ATMEL_BASE_SPI1 0xfffcc000 +#define ATMEL_BASE_USART3 0xfffd0000 +#define ATMEL_BASE_USART4 0xfffd4000 +/* USART5 or TWI1: 0xfffd8000 */ +#define ATMEL_BASE_TCB1 0xfffdc000 +#define ATMEL_BASE_TC3 0xfffdc000 +#define ATMEL_BASE_TC4 0xfffdc040 +#define ATMEL_BASE_TC5 0xfffdc080 +#define ATMEL_BASE_ADC 0xfffe0000 +/* Reserved: 0xfffe4000 - 0xffffe7ff */ /* - * System Peripherals (offset from AT91_BASE_SYS) + * System Peripherals physical base addresses. */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9260_BASE_US0 -#define AT91_USART1 AT91SAM9260_BASE_US1 -#define AT91_USART2 AT91SAM9260_BASE_US2 -#define AT91_USART3 AT91SAM9260_BASE_US3 -#define AT91_USART4 AT91SAM9260_BASE_US4 -#define AT91_USART5 AT91SAM9260_BASE_US5 - -#endif /* CONFIG_AT91_LEGACY */ +#define ATMEL_BASE_SYS 0xffffe800 +#define ATMEL_BASE_SDRAMC 0xffffea00 +#define ATMEL_BASE_SMC 0xffffec00 +#define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +/* EEFC: 0xfffffa00 */ +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +/* GPBR(non-XE SoCs): 0xfffffd50 */ +/* GPBR(XE SoCs): 0xfffffd60 */ +/* Reserved: 0xfffffd70 - 0xffffffff */ /* - * Internal Memory. + * Internal Memory common on all these SoCs */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ +#define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */ +#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ +/* SRAM or FLASH: 0x00200000 */ +/* SRAM: 0x00300000 */ +/* Reserved: 0x00400000 */ +#define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* - * Cpu Name + * SoC specific defines */ #if defined(CONFIG_AT91SAM9XE) -# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9XE" +# define ATMEL_CPU_NAME "AT91SAM9XE" +# define ATMEL_ID_TWI1 25 /* TWI 1 */ +# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */ +# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */ +# define ATMEL_BASE_TWI1 0xfffd8000 +# define ATMEL_BASE_EEFC 0xfffffa00 +# define ATMEL_BASE_GPBR 0xfffffd60 #elif defined(CONFIG_AT91SAM9260) -# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" +# define ATMEL_CPU_NAME "AT91SAM9260" +# define ATMEL_ID_USART5 25 /* USART 5 */ +# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ +# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ +# define ATMEL_BASE_USART5 0xfffd8000 +# define ATMEL_BASE_GPBR 0xfffffd50 #elif defined(CONFIG_AT91SAM9G20) -# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" +# define ATMEL_CPU_NAME "AT91SAM9G20" +# define ATMEL_ID_USART5 25 /* USART 5 */ +# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ +# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ +# define ATMEL_BASE_USART5 0xfffd8000 +# define ATMEL_BASE_GPBR 0xfffffd50 #endif #endif -- cgit v1.2.3 From 5e5925930bf26236563828bcd65577ba6fcb6841 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Fri, 19 Nov 2010 10:04:37 +0100 Subject: AT91: rework at91sam9261.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91sam9261.h | 187 +++++++++++++++------------ 1 file changed, 102 insertions(+), 85 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index 7ca0283135..f8048d5612 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -2,9 +2,15 @@ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] * * Copyright (C) SAN People + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) + * Definitions for the SoCs: + * AT91SAM9261, AT91SAM9G10 + * + * Note that those SoCs are mostly software and pin compatible, + * therefore this file applies to all of them. Differences between + * those SoCs are concentrated at the end of this file. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,106 +22,117 @@ #define AT91SAM9261_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_RTT_BASE 0xfffffd20 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 -#define AT91_GPBR_BASE 0xfffffd50 +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ +/* Reserved: 5 */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_USART2 8 /* USART 2 */ +#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ +#define ATMEL_ID_UDP 10 /* USB Device Port */ +#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ +#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ +#define ATMEL_ID_UHP 20 /* USB Host port */ +#define ATMEL_ID_LCDC 21 /* LDC Controller */ +/* Reserved: 22-28 */ +#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ -#ifdef CONFIG_AT91_LEGACY +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_TCB0 0xfffa0000 +#define ATMEL_BASE_TC0 0xfffa0000 +#define ATMEL_BASE_TC1 0xfffa0040 +#define ATMEL_BASE_TC2 0xfffa0080 +#define ATMEL_BASE_UDP0 0xfffa4000 +#define ATMEL_BASE_MCI 0xfffa8000 +#define ATMEL_BASE_TWI0 0xfffac000 +#define ATMEL_BASE_USART0 0xfffb0000 +#define ATMEL_BASE_USART1 0xfffb4000 +#define ATMEL_BASE_USART2 0xfffb8000 +#define ATMEL_BASE_SSC0 0xfffbc000 +#define ATMEL_BASE_SSC1 0xfffc0000 +#define ATMEL_BASE_SSC2 0xfffc4000 +#define ATMEL_BASE_SPI0 0xfffc8000 +#define ATMEL_BASE_SPI1 0xfffcc000 +/* Reserved: 0xfffc4000 - 0xffffe9ff */ /* - * User Peripheral physical base addresses. + * System Peripherals physical base addresses. */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00 +#define ATMEL_BASE_SYS 0xffffea00 +#define ATMEL_BASE_SDRAMC 0xffffea00 +#define ATMEL_BASE_SMC 0xffffec00 +#define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_GPBR 0xfffffd50 /* - * System Peripherals (offset from AT91_BASE_SYS) + * Internal Memory common on all these SoCs */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */ -#define AT91_USART0 AT91SAM9261_BASE_US0 -#define AT91_USART1 AT91SAM9261_BASE_US1 -#define AT91_USART2 AT91SAM9261_BASE_US2 +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ +#define ATMEL_SIZE_ROM SZ_32K /* Internal ROM size (32Kb) */ -#endif /* CONFIG_AT91_LEGACY */ +#define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */ +#define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */ /* - * Internal Memory. + * External memory */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ +#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ /* - * Cpu Name + * SoC specific defines */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" +#if defined(CONFIG_AT91SAM9261) +# define ATMEL_CPU_NAME "AT91SAM9261" +#elif defined(CONFIG_AT91SAM9G10) +# define ATMEL_CPU_NAME "AT91SAM9G10" +#endif #endif -- cgit v1.2.3 From 09aca70fa4628ef69a1968d3ae8bbad82fd2edad Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Fri, 19 Nov 2010 10:05:01 +0100 Subject: AT91: rework at91sam9263.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91sam9263.h | 218 ++++++++++++--------------- 1 file changed, 100 insertions(+), 118 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index 4ada1ceaf8..bfd408bb1d 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -2,9 +2,11 @@ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] * * (C) 2007 Atmel Corporation. + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). + * Definitions for the SoC: + * AT91SAM9263 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,140 +18,120 @@ #define AT91SAM9263_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_ECC0_BASE 0xffffe000 -#define AT91_SDRAMC0_BASE 0xffffe200 -#define AT91_SMC0_BASE 0xffffe400 -#define AT91_ECC1_BASE 0xffffe600 -#define AT91_SDRAMC1_BASE 0xffffe800 -#define AT91_SMC1_BASE 0xffffea00 -#define AT91_MATRIX_BASE 0xffffec00 -#define AT91_CCFG_BASE 0xffffed10 -#define AT91_DBGU_BASE 0xffffee00 -#define AT91_AIC_BASE 0xfffff000 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_RTT0_BASE 0xfffffd20 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 -#define AT91_RTT1_BASE 0xfffffd50 -#define AT91_GPBR_BASE 0xfffffd60 - -#ifdef CONFIG_AT91_LEGACY +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* - * User Peripheral physical base addresses. + * Peripheral identifiers/interrupts. */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 -#define AT91_BASE_SYS 0xffffe000 +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ +/* Reserved: 5 */ +/* Reserved: 6 */ +#define ATMEL_ID_USART0 7 /* USART 0 */ +#define ATMEL_ID_USART1 8 /* USART 1 */ +#define ATMEL_ID_USART2 9 /* USART 2 */ +#define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */ +#define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */ +#define ATMEL_ID_CAN 12 /* CAN */ +#define ATMEL_ID_TWI 13 /* Two-Wire Interface */ +#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_AC97C 18 /* AC97 Controller */ +#define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ +#define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_EMAC 21 /* Ethernet */ +/* Reserved: 22 */ +#define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */ +#define ATMEL_ID_UDP 24 /* USB Device Port */ +#define ATMEL_ID_ISI 25 /* Image Sensor Interface */ +#define ATMEL_ID_LCDC 26 /* LCD Controller */ +#define ATMEL_ID_DMA 27 /* DMA Controller */ +/* Reserved: 28 */ +#define ATMEL_ID_UHP 29 /* USB Host port */ +#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ /* - * System Peripherals (offset from AT91_BASE_SYS) + * User Peripherals physical base addresses. */ -#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) -#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) -#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9263_BASE_US0 -#define AT91_USART1 AT91SAM9263_BASE_US1 -#define AT91_USART2 AT91SAM9263_BASE_US2 - -#define AT91_SMC AT91_SMC0 -#define AT91_SDRAMC AT91_SDRAMC0 +#define ATMEL_BASE_UDP 0xfff78000 +#define ATMEL_BASE_TCB0 0xfff7c000 +#define ATMEL_BASE_TC0 0xfff7c000 +#define ATMEL_BASE_TC1 0xfff7c040 +#define ATMEL_BASE_TC2 0xfff7c080 +#define ATMEL_BASE_MCI0 0xfff80000 +#define ATMEL_BASE_MCI1 0xfff84000 +#define ATMEL_BASE_TWI 0xfff88000 +#define ATMEL_BASE_USART0 0xfff8c000 +#define ATMEL_BASE_USART1 0xfff90000 +#define ATMEL_BASE_USART2 0xfff94000 +#define ATMEL_BASE_SSC0 0xfff98000 +#define ATMEL_BASE_SSC1 0xfff9c000 +#define ATMEL_BASE_AC97C 0xfffa0000 +#define ATMEL_BASE_SPI0 0xfffa4000 +#define ATMEL_BASE_SPI1 0xfffa8000 +#define ATMEL_BASE_CAN 0xfffac000 +#define ATMEL_BASE_PWMC 0xfffb8000 +#define ATMEL_BASE_EMAC 0xfffbc000 +#define ATMEL_BASE_ISI 0xfffc4000 +#define ATMEL_BASE_2DGE 0xfffc8000 -#endif /* CONFIG_AT91_LEGACY */ +/* + * System Peripherals physical base addresses. + */ +#define ATMEL_BASE_ECC0 0xffffe000 +#define ATMEL_BASE_SDRAMC0 0xffffe200 +#define ATMEL_BASE_SMC0 0xffffe400 +#define ATMEL_BASE_ECC1 0xffffe600 +#define ATMEL_BASE_SDRAMC1 0xffffe800 +#define ATMEL_BASE_SMC1 0xffffea00 +#define ATMEL_BASE_MATRIX 0xffffec00 +#define ATMEL_BASE_CCFG 0xffffed10 +#define ATMEL_BASE_DBGU 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_PIOA 0xfffff200 +#define ATMEL_BASE_PIOB 0xfffff400 +#define ATMEL_BASE_PIOC 0xfffff600 +#define ATMEL_BASE_PIOD 0xfffff800 +#define ATMEL_BASE_PIOE 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWC 0xfffffd10 +#define ATMEL_BASE_RTT0 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_RTT1 0xfffffd50 +#define ATMEL_BASE_GPBR 0xfffffd60 /* * Internal Memory. */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ +#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */ + +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */ -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ +#define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */ -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ +#define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */ +#define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */ +#define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */ -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ /* * Cpu Name */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" +#define ATMEL_CPU_NAME "AT91SAM9263" #endif -- cgit v1.2.3 From 4b1f9b1b367a08364e0c74dfbc91d986eff23684 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Fri, 18 Feb 2011 09:33:51 +0100 Subject: AT91: rework at91sam9g45.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91sam9g45.h | 225 +++++++++++++-------------- 1 file changed, 107 insertions(+), 118 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 445f4b2123..364b86c88f 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -1,10 +1,10 @@ /* * Chip-specific header file for the AT91SAM9M1x family * - * Copyright (C) 2008 Atmel Corporation. + * (C) 2008 Atmel Corporation. * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. + * Definitions for the SoC: + * AT91SAM9G45 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,137 +16,126 @@ #define AT91SAM9G45_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller Interrupt */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_SMC_BASE 0xffffe800 -#define AT91_MATRIX_BASE 0xffffea00 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* - * User Peripheral physical base addresses. + * Peripheral identifiers/interrupts. */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 -#define AT91_BASE_SYS 0xffffe200 +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ +#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */ +#define ATMEL_ID_TRNG 6 /* True Random Number Generator */ +#define ATMEL_ID_USART0 7 /* USART 0 */ +#define ATMEL_ID_USART1 8 /* USART 1 */ +#define ATMEL_ID_USART2 9 /* USART 2 */ +#define ATMEL_ID_USART3 10 /* USART 3 */ +#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ +#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */ +#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */ +#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */ +#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */ +#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */ +#define ATMEL_ID_DMA 21 /* DMA Controller */ +#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ +#define ATMEL_ID_LCDC 23 /* LCD Controller */ +#define ATMEL_ID_AC97C 24 /* AC97 Controller */ +#define ATMEL_ID_EMAC 25 /* Ethernet MAC */ +#define ATMEL_ID_ISI 26 /* Image Sensor Interface */ +#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */ +#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ +#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ +#define ATMEL_ID_VDEC 30 /* Video Decoder */ +#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */ /* - * System Peripherals (offset from AT91_BASE_SYS) + * User Peripherals physical base addresses. */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) -#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9G45_BASE_US0 -#define AT91_USART1 AT91SAM9G45_BASE_US1 -#define AT91_USART2 AT91SAM9G45_BASE_US2 -#define AT91_USART3 AT91SAM9G45_BASE_US3 +#define ATMEL_BASE_UDPHS 0xfff78000 +#define ATMEL_BASE_TC0 0xfff7c000 +#define ATMEL_BASE_TC1 0xfff7c040 +#define ATMEL_BASE_TC2 0xfff7c080 +#define ATMEL_BASE_MCI0 0xfff80000 +#define ATMEL_BASE_TWI0 0xfff84000 +#define ATMEL_BASE_TWI1 0xfff88000 +#define ATMEL_BASE_USART0 0xfff8c000 +#define ATMEL_BASE_USART1 0xfff90000 +#define ATMEL_BASE_USART2 0xfff94000 +#define ATMEL_BASE_USART3 0xfff98000 +#define ATMEL_BASE_SSC0 0xfff9c000 +#define ATMEL_BASE_SSC1 0xfffa0000 +#define ATMEL_BASE_SPI0 0xfffa4000 +#define ATMEL_BASE_SPI1 0xfffa8000 +#define ATMEL_BASE_AC97C 0xfffac000 +#define ATMEL_BASE_TSC 0xfffb0000 +#define ATMEL_BASE_ISI 0xfffb4000 +#define ATMEL_BASE_PWMC 0xfffb8000 +#define ATMEL_BASE_EMAC 0xfffbc000 +#define ATMEL_BASE_AES 0xfffc0000 +#define ATMEL_BASE_TDES 0xfffc4000 +#define ATMEL_BASE_SHA 0xfffc8000 +#define ATMEL_BASE_TRNG 0xfffcc000 +#define ATMEL_BASE_MCI1 0xfffd0000 +#define ATMEL_BASE_TC3 0xfffd4000 +#define ATMEL_BASE_TC4 0xfffd4040 +#define ATMEL_BASE_TC5 0xfffd4080 +/* Reserved: 0xfffd8000 - 0xffffe1ff */ -#endif +/* + * System Peripherals physical base addresses. + */ +#define ATMEL_BASE_SYS 0xffffe200 +#define ATMEL_BASE_ECC 0xffffe200 +#define ATMEL_BASE_DDRSDRC1 0xffffe400 +#define ATMEL_BASE_DDRSDRC0 0xffffe600 +#define ATMEL_BASE_SMC 0xffffe800 +#define ATMEL_BASE_MATRIX 0xffffea00 +#define ATMEL_BASE_DMA 0xffffec00 +#define ATMEL_BASE_DBGU 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_PIOA 0xfffff200 +#define ATMEL_BASE_PIOB 0xfffff400 +#define ATMEL_BASE_PIOC 0xfffff600 +#define ATMEL_BASE_PIOD 0xfffff800 +#define ATMEL_BASE_PIOE 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_GPBR 0xfffffd60 +#define ATMEL_BASE_RTC 0xfffffdb0 +/* Reserved: 0xfffffdc0 - 0xffffffff */ /* * Internal Memory. */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ +#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ +#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ +#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */ +#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ /* * Cpu Name */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" +#define ATMEL_CPU_NAME "AT91SAM9G45" #endif -- cgit v1.2.3 From 405e5919f28ab0a6955b74dd8123331a5d4c4ab1 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Wed, 3 Nov 2010 11:30:23 +0100 Subject: AT91: cleanup hardware.h, remove memory-map.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/hardware.h | 96 ++++++++++------------------- arch/arm/include/asm/arch-at91/memory-map.h | 36 ----------- 2 files changed, 32 insertions(+), 100 deletions(-) delete mode 100644 arch/arm/include/asm/arch-at91/memory-map.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index 6b44d61207..36af571a5b 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -1,80 +1,48 @@ /* - * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL + * See file CREDITS for list of people who contributed to this + * project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include +#ifndef __ASM_ARM_ARCH_HARDWARE_H__ +#define __ASM_ARM_ARCH_HARDWARE_H__ #if defined(CONFIG_AT91RM9200) -#include -#define AT91_PMC_UHP AT91RM9200_PMC_UHP -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#include -#define AT91_BASE_MCI AT91SAM9260_BASE_MCI -#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 -#define AT91_BASE_SPI1 AT91SAM9260_BASE_SPI1 -#define AT91_ID_UHP AT91SAM9260_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \ + defined(CONFIG_AT91SAM9XE) +# include #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) -#include -#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9261_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include #elif defined(CONFIG_AT91SAM9263) -#include -#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9263_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include #elif defined(CONFIG_AT91SAM9RL) -#include -#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI -#define AT91_ID_UHP AT91SAM9RL_ID_UHP +# include #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) -#include -#define AT91_BASE_EMAC AT91SAM9G45_BASE_EMAC -#define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9G45_ID_UHPHS -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include #elif defined(CONFIG_AT91CAP9) -#include -#define AT91_BASE_SPI AT91CAP9_BASE_SPI0 -#define AT91_ID_UHP AT91CAP9_ID_UHP -#define AT91_PMC_UHP AT91CAP9_PMC_UHP +# include #elif defined(CONFIG_AT91X40) -#include +# include #else -#error "Unsupported AT91 processor" +# error "Unsupported AT91 processor" #endif -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -/* SDRAM */ -#ifdef CONFIG_DRAM_BASE -#define AT91_SDRAM_BASE CONFIG_DRAM_BASE -#else -#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 -#endif - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#endif +#endif /* __ASM_ARM_ARCH_HARDWARE_H__ */ diff --git a/arch/arm/include/asm/arch-at91/memory-map.h b/arch/arm/include/asm/arch-at91/memory-map.h deleted file mode 100644 index d489fa2157..0000000000 --- a/arch/arm/include/asm/arch-at91/memory-map.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__ -#define __ASM_ARM_ARCH_MEMORYMAP_H__ - -#include - -#define USART0_BASE AT91_USART0 -#define USART1_BASE AT91_USART1 -#define USART2_BASE AT91_USART2 -#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) -#define SPI0_BASE AT91_BASE_SPI -#define SPI1_BASE AT91_BASE_SPI1 - -#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ -- cgit v1.2.3 From 83f1072e06d4e3b9eaceed39799042c7b3bbdbb1 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Wed, 3 Nov 2010 15:38:33 +0100 Subject: AT91: fix related arch-at91 header files Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91_common.h | 3 +-- arch/arm/include/asm/arch-at91/at91_pio.h | 19 +++---------------- arch/arm/include/asm/arch-at91/gpio.h | 18 +++++++++--------- arch/arm/include/asm/arch-at91/io.h | 4 ++-- 4 files changed, 15 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 0067190a20..330edd83c5 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -28,11 +28,10 @@ void at91_can_hw_init(void); void at91_macb_hw_init(void); void at91_mci_hw_init(void); -void at91_serial_hw_init(void); void at91_serial0_hw_init(void); void at91_serial1_hw_init(void); void at91_serial2_hw_init(void); -void at91_serial3_hw_init(void); +void at91_seriald_hw_init(void); void at91_spi0_hw_init(unsigned long cs_mask); void at91_spi1_hw_init(unsigned long cs_mask); void at91_uhp_hw_init(void); diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index f7915a3322..0b5bd69db8 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -76,32 +76,19 @@ typedef struct at91_port { u32 reserved6[85]; } at91_port_t; -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20) -#define AT91_PIO_PORTS 3 -#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ - defined(CONFIG_AT91SAM9M10G45) -#define AT91_PIO_PORTS 5 -#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \ - defined(CONFIG_AT91SAM9RL) -#define AT91_PIO_PORTS 4 -#else -#error "Unsupported cpu. Please update at91_pio.h" -#endif - typedef union at91_pio { struct { at91_port_t pioa; at91_port_t piob; at91_port_t pioc; - #if (AT91_PIO_PORTS > 3) + #if (ATMEL_PIO_PORTS > 3) at91_port_t piod; #endif - #if (AT91_PIO_PORTS > 4) + #if (ATMEL_PIO_PORTS > 4) at91_port_t pioe; #endif } ; - at91_port_t port[AT91_PIO_PORTS]; + at91_port_t port[ATMEL_PIO_PORTS]; } at91_pio_t; #ifdef CONFIG_AT91_GPIO diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h index 716f81fa3c..293d0bf56b 100644 --- a/arch/arm/include/asm/arch-at91/gpio.h +++ b/arch/arm/include/asm/arch-at91/gpio.h @@ -18,7 +18,7 @@ #include #include -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #define PIN_BASE 32 @@ -192,13 +192,13 @@ #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) static unsigned long at91_pios[] = { - AT91_PIOA, - AT91_PIOB, - AT91_PIOC, -#ifdef AT91_PIOD - AT91_PIOD, -#ifdef AT91_PIOE - AT91_PIOE + ATMEL_BASE_PIOA, + ATMEL_BASE_PIOB, + ATMEL_BASE_PIOC, +#ifdef ATMEL_BASE_PIOD + ATMEL_BASE_PIOD, +#ifdef ATMEL_BASE_PIOE + ATMEL_BASE_PIOE #endif #endif }; @@ -207,7 +207,7 @@ static inline void *pin_to_controller(unsigned pin) { pin -= PIN_BASE; pin /= 32; - return (void *)(AT91_BASE_SYS + at91_pios[pin]); + return (void *)(at91_pios[pin]); } static inline unsigned pin_to_mask(unsigned pin) diff --git a/arch/arm/include/asm/arch-at91/io.h b/arch/arm/include/asm/arch-at91/io.h index 38d185eb7c..d0daa4ece5 100644 --- a/arch/arm/include/asm/arch-at91/io.h +++ b/arch/arm/include/asm/arch-at91/io.h @@ -27,14 +27,14 @@ static inline unsigned int at91_sys_read(unsigned int reg_offset) { - void *addr = (void *)AT91_BASE_SYS; + void *addr = (void *)ATMEL_BASE_SYS; return __raw_readl(addr + reg_offset); } static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) { - void *addr = (void *)AT91_BASE_SYS; + void *addr = (void *)ATMEL_BASE_SYS; __raw_writel(value, addr + reg_offset); } -- cgit v1.2.3 From 9f3fe90f094d4ad6309b5222196d0f8c783784b0 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Wed, 3 Nov 2010 15:39:55 +0100 Subject: AT91: fix related at91 system/driver files Signed-off-by: Reinhard Meyer --- arch/arm/cpu/arm926ejs/at91/Makefile | 1 + arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 45 +++++++---------------- arch/arm/cpu/arm926ejs/at91/clock.c | 6 +-- arch/arm/cpu/arm926ejs/at91/cpu.c | 8 ++-- arch/arm/cpu/arm926ejs/at91/eflash.c | 14 +++---- arch/arm/cpu/arm926ejs/at91/reset.c | 2 +- arch/arm/cpu/arm926ejs/at91/timer.c | 8 ++-- 7 files changed, 33 insertions(+), 51 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index be9f6dddf0..f333753c71 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_AT91CAP9) += at91cap9_devices.o COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o +COBJS-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index c1822b713d..54e8ee90fe 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -45,70 +45,51 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */ - writel(1 << AT91SAM9260_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */ - writel(1 << AT91SAM9260_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */ - writel(1 << AT91SAM9260_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -138,14 +119,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 7a10a77877..06c63e545b 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -57,7 +57,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return AT91_SLOW_CLOCK; + return CONFIG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -145,7 +145,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; #ifndef CONFIG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* @@ -159,7 +159,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->main_clk_rate_hz = main_clock; diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c index 5e30f1dccc..4c8664d659 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/cpu/arm926ejs/at91/cpu.c @@ -44,7 +44,7 @@ int arch_cpu_init(void) void arch_preboot_os(void) { ulong cpiv; - at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); @@ -61,7 +61,7 @@ int print_cpuinfo(void) { char buf[32]; - printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME); + printf("CPU: %s\n", ATMEL_CPU_NAME); printf("Crystal frequency: %8s MHz\n", strmhz(buf, get_main_clk_rate())); printf("CPU clock : %8s MHz\n", @@ -80,7 +80,7 @@ int print_cpuinfo(void) */ void bootcount_store (ulong a) { - at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff), &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); @@ -88,7 +88,7 @@ void bootcount_store (ulong a) ulong bootcount_load (void) { - at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c index 938c3b1f05..a6e0501bb9 100644 --- a/arch/arm/cpu/arm926ejs/at91/eflash.c +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -77,8 +77,8 @@ static u32 pagesize; unsigned long flash_init (void) { - at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; - at91_dbu_t *dbu = (at91_dbu_t *) 0xfffff200; + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; + at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU; u32 id, size, nplanes, planesize, nlocks; u32 addr, i, tmp=0; @@ -119,7 +119,7 @@ unsigned long flash_init (void) flash_info[0].sector_count = nlocks; flash_info[0].flash_id = id; - addr = AT91SAM9XE_FLASH_BASE; + addr = ATMEL_BASE_FLASH; for (i=0; ifrr); /* words 4+nplanes+1.. */ flash_info[0].start[i] = addr; @@ -167,8 +167,8 @@ void flash_print_info (flash_info_t *info) int flash_real_protect (flash_info_t *info, long sector, int prot) { - at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; - u32 pagenum = (info->start[sector]-AT91SAM9XE_FLASH_BASE)/pagesize; + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; + u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize; u32 i, tmp=0; debug("protect sector=%ld prot=%d\n", sector, prot); @@ -205,7 +205,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot) static u32 erase_write_page (u32 pagenum) { - at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; debug("erase+write page=%u\n", pagenum); @@ -249,7 +249,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) } /* now start copying data */ - pagenum = (addr-AT91SAM9XE_FLASH_BASE)/pagesize; + pagenum = (addr-ATMEL_BASE_FLASH)/pagesize; src32 = (u32 *) src; dst32 = (u32 *) addr; while (cnt > 0) { diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index d2569d8bae..1f918b0e94 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -30,7 +30,7 @@ /* Reset the cpu by telling the reset controller to do so */ void reset_cpu(ulong ignored) { - at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST /* Processor Reset */ diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index 82b8d7e7d7..263441810b 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -70,11 +70,11 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) */ int timer_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; /* Enable PITC Clock */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); @@ -90,7 +90,7 @@ int timer_init(void) */ unsigned long long get_ticks(void) { - at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; ulong now = readl(&pit->piir); -- cgit v1.2.3 From 60af56803878ab35598fe4267ff55e7471148999 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Sun, 7 Nov 2010 12:38:43 +0100 Subject: AT91: cleanup at91sam9260_matrix.h to struct SoC access Signed-off-by: Reinhard Meyer --- .../arm/include/asm/arch-at91/at91sam9260_matrix.h | 102 +++++++++------------ 1 file changed, 45 insertions(+), 57 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h index f8b023d932..be28ad1c1d 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h @@ -15,66 +15,54 @@ #ifndef AT91SAM9260_MATRIX_H #define AT91SAM9260_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +/* + * This struct defines access to the matrix' maximum of + * 16 masters and 16 slaves. + * However, on the AT91SAM9260/9G20/9XE there exist only + * 6 Masters and 5 Slaves! + */ +struct at91_matrix { + u32 mcfg[16]; /* Master Configuration Registers */ + u32 scfg[16]; /* Slave Configuration Registers */ + u32 pras[16][2]; /* Priority Assignment Slave Registers */ + u32 mrcr; /* Master Remap Control Register */ + u32 filler[0x06]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; + +#endif /* __ASSEMBLY__ */ + +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif -- cgit v1.2.3 From 86592f60595f5dcebde01c9a4135485fbf2a61d6 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Sun, 7 Nov 2010 13:26:14 +0100 Subject: AT91: change includes from asm/arch/io.h to asm/io.h and remove the now unused asm/arch-at91/io.h Signed-off-by: Reinhard Meyer --- arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 2 +- arch/arm/cpu/arm926ejs/at91/clock.c | 2 +- arch/arm/cpu/arm926ejs/at91/cpu.c | 3 +- arch/arm/cpu/arm926ejs/at91/eflash.c | 2 +- arch/arm/cpu/arm926ejs/at91/led.c | 2 +- arch/arm/cpu/arm926ejs/at91/reset.c | 2 +- arch/arm/cpu/arm926ejs/at91/timer.c | 2 +- arch/arm/include/asm/arch-at91/io.h | 43 ----------------------- 8 files changed, 7 insertions(+), 51 deletions(-) delete mode 100644 arch/arm/include/asm/arch-at91/io.h (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index 54e8ee90fe..6bdc75c702 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -23,10 +23,10 @@ */ #include +#include #include #include #include -#include /* * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 06c63e545b..608af2cf72 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -12,8 +12,8 @@ */ #include +#include #include -#include #include #include diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c index 4c8664d659..c47fb31e99 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/cpu/arm926ejs/at91/cpu.c @@ -24,13 +24,12 @@ */ #include - +#include #include #include #include #include #include -#include #ifndef CONFIG_SYS_AT91_MAIN_CLOCK #define CONFIG_SYS_AT91_MAIN_CLOCK 0 diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c index a6e0501bb9..b0c1e1e814 100644 --- a/arch/arm/cpu/arm926ejs/at91/eflash.c +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -60,8 +60,8 @@ * do a read-modify-write for partially programmed pages */ #include +#include #include -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c index 0a315c4971..6bcfa7f2fd 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/cpu/arm926ejs/at91/led.c @@ -23,10 +23,10 @@ */ #include +#include #include #include #include -#include #ifdef CONFIG_RED_LED void red_LED_on(void) diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index 1f918b0e94..023719a683 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -23,9 +23,9 @@ */ #include +#include #include #include -#include /* Reset the cpu by telling the reset controller to do so */ void reset_cpu(ulong ignored) diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index 263441810b..87a5b633a4 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -23,11 +23,11 @@ */ #include +#include #include #include #include #include -#include #include #if !defined(CONFIG_AT91FAMILY) diff --git a/arch/arm/include/asm/arch-at91/io.h b/arch/arm/include/asm/arch-at91/io.h deleted file mode 100644 index d0daa4ece5..0000000000 --- a/arch/arm/include/asm/arch-at91/io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/io.h] - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include - -#ifdef CONFIG_AT91_LEGACY - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void *addr = (void *)ATMEL_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void *addr = (void *)ATMEL_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif - -#endif -- cgit v1.2.3 From 50f750022b0cab3b047b9544d3ce769708f2bd78 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Wed, 10 Nov 2010 18:08:47 +0100 Subject: AT91: remove LEGACY from at91_rstc.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91_rstc.h | 25 ------------------------- 1 file changed, 25 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h index 9ff2c5b7ac..510eed5840 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/include/asm/arch-at91/at91_rstc.h @@ -41,29 +41,4 @@ typedef struct at91_rstc { #define AT91_RSTC_SR_NRSTL 0x00010000 -#ifdef CONFIG_AT91_LEGACY - -#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ - -#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ - -#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ - -#endif /* CONFIG_AT91_LEGACY */ - #endif -- cgit v1.2.3 From cfff263f41e32c7ba2ee9162a8cc6423eb5a8390 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Wed, 10 Nov 2010 18:07:56 +0100 Subject: AT91: fix timer.c - remove reset_timer() Signed-off-by: Reinhard Meyer --- arch/arm/cpu/arm926ejs/at91/timer.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index 87a5b633a4..a0876879d3 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -103,33 +103,28 @@ unsigned long long get_ticks(void) void __udelay(unsigned long usec) { - unsigned long long tmp; + unsigned long long start; ulong tmo; - tmo = usec_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - ; + start = get_ticks(); /* get current timestamp */ + tmo = usec_to_tick(usec); /* convert usecs to ticks */ + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ } /* - * reset_timer() and get_timer(base) are a pair of functions that are used by - * some timeout/sleep mechanisms in u-boot. + * get_timer(base) can be used to check for timeouts or + * to measure elasped time relative to an event: * - * reset_timer() marks the current time as epoch and - * get_timer(base) works relative to that epoch. + * ulong start_time = get_timer(0) sets start_time to the current + * time value. + * get_timer(start_time) returns the time elapsed since then. * * The time is used in CONFIG_SYS_HZ units! */ -void reset_timer(void) -{ - gd->timer_reset_value = get_ticks(); -} - ulong get_timer(ulong base) { - return tick_to_time(get_ticks() - gd->timer_reset_value) - base; + return tick_to_time(get_ticks()) - base; } /* -- cgit v1.2.3 From ce26582606adda28b3cd1a5d7646bbaa3a300937 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Sat, 18 Dec 2010 02:30:04 +0000 Subject: at91rm9200: fix lowlevel_init() SMRDATA size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * use start/end label for initialization tables instead of fix values Signed-off-by: Jens Scharsig Acked-by: Andreas Bießmann --- arch/arm/cpu/arm920t/at91/lowlevel_init.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S index eaea9d2535..8b58ba9fa5 100644 --- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/at91/lowlevel_init.S @@ -65,7 +65,8 @@ LoopOsc: ldr r0, =SMRDATA ldr r1, _MTEXT_BASE sub r0, r0, r1 - add r2, r0, #80 + ldr r2, =SMRDATAE + sub r2, r2, r1 pllloop: /* the address */ ldr r1, [r0], #4 @@ -83,7 +84,8 @@ lock: ldr r0, =SMRDATA1 ldr r1, _MTEXT_BASE sub r0, r0, r1 - add r2, r0, #176 + ldr r2, =SMRDATA1E + sub r2, r2, r1 sdinit: /* the address */ ldr r1, [r0], #4 @@ -114,6 +116,7 @@ SMRDATA: .word CONFIG_SYS_PLLBR_VAL .word AT91_ASM_PMC_MCKR .word CONFIG_SYS_MCKR_VAL +SMRDATAE: /* here there's a delay */ SMRDATA1: .word AT91_ASM_PIOC_ASR @@ -160,5 +163,6 @@ SMRDATA1: .word CONFIG_SYS_SDRC_MR_VAL3 .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL +SMRDATA1E: /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -- cgit v1.2.3 From 673678eacf35abac3e9d2cb5dca9b15433e21080 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Wed, 22 Dec 2010 01:16:47 +0000 Subject: remove __attribute__ ((packed)) in at91 headers * remove __attribute__ ((packed)) to prevent byte access to soc registers in some gcc version Signed-off-by: Jens Scharsig --- arch/arm/include/asm/arch-at91/at91_mc.h | 10 +++++----- arch/arm/include/asm/arch-at91/at91_st.h | 2 +- arch/arm/include/asm/arch-at91/at91_tc.h | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91_mc.h b/arch/arm/include/asm/arch-at91/at91_mc.h index acfbd10c5c..09453a9450 100644 --- a/arch/arm/include/asm/arch-at91/at91_mc.h +++ b/arch/arm/include/asm/arch-at91/at91_mc.h @@ -36,7 +36,7 @@ typedef struct at91_ebi { u32 csa; /* 0x00 Chip Select Assignment Register */ u32 cfgr; /* 0x04 Configuration Register */ u32 reserved[2]; -} __attribute__ ((packed)) at91_ebi_t; +} at91_ebi_t; #define AT91_EBI_CSA_CS0A 0x0001 #define AT91_EBI_CSA_CS1A 0x0002 @@ -55,11 +55,11 @@ typedef struct at91_sdramc { u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ u32 reserved[3]; -} __attribute__ ((packed)) at91_sdramc_t; +} at91_sdramc_t; typedef struct at91_smc { u32 csr[8]; /* 0x00 SDRAMC Mode Register */ -} __attribute__ ((packed)) at91_smc_t; +} at91_smc_t; #define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) #define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) @@ -78,7 +78,7 @@ typedef struct at91_smc { typedef struct at91_bfc { u32 mr; /* 0x00 SDRAMC Mode Register */ -} __attribute__ ((packed)) at91_bfc_t; +} at91_bfc_t; typedef struct at91_mc { u32 rcr; /* 0x00 MC Remap Control Register */ @@ -91,7 +91,7 @@ typedef struct at91_mc { at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ at91_bfc_t bfc; /* 0xC0 BFC User Interface */ u32 reserved2[15]; -} __attribute__ ((packed)) at91_mc_t; +} at91_mc_t; #endif #endif diff --git a/arch/arm/include/asm/arch-at91/at91_st.h b/arch/arm/include/asm/arch-at91/at91_st.h index 53f932085b..98b0a7640b 100644 --- a/arch/arm/include/asm/arch-at91/at91_st.h +++ b/arch/arm/include/asm/arch-at91/at91_st.h @@ -35,7 +35,7 @@ typedef struct at91_st { u32 imr; u32 rtar; u32 crtr; -} __attribute__ ((packed)) at91_st_t ; +} at91_st_t ; #define AT91_ST_CR_WDRST 1 diff --git a/arch/arm/include/asm/arch-at91/at91_tc.h b/arch/arm/include/asm/arch-at91/at91_tc.h index 1e180adb3c..1eae4e95c7 100644 --- a/arch/arm/include/asm/arch-at91/at91_tc.h +++ b/arch/arm/include/asm/arch-at91/at91_tc.h @@ -36,7 +36,7 @@ typedef struct at91_tcc { u32 idr; /* 0x28 Interrupt Disable Register */ u32 imr; /* 0x2C Interrupt Mask Register */ u32 reserved3[4]; -} __attribute__ ((packed)) at91_tcc_t; +} at91_tcc_t; #define AT91_TC_CCR_CLKEN 0x00000001 #define AT91_TC_CCR_CLKDIS 0x00000002 @@ -57,7 +57,7 @@ typedef struct at91_tc { at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ u32 bcr; /* 0xC0 TC Block Control Register */ u32 bmr; /* 0xC4 TC Block Mode Register */ -} __attribute__ ((packed)) at91_tc_t; +} at91_tc_t; #define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 #define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 -- cgit v1.2.3 From 1069a5cf308be64882caeb141c9002928c9f1d70 Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Thu, 20 Jan 2011 23:12:15 +0000 Subject: at91: fixed at91sam9263 system file Signed-off-by: Daniel Gorsulowski --- arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c | 55 ++++++++--------------- 1 file changed, 18 insertions(+), 37 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index deda3e54d9..15e880accd 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -3,7 +3,7 @@ * Stelian Pop * Lead Tech Design * - * (C) Copyright 2009 + * (C) Copyright 2009-2011 * Daniel Gorsulowski * esd electronic system design gmbh * @@ -27,78 +27,59 @@ */ #include +#include #include -#include #include #include #include void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ - writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ - writel(1 << AT91SAM9263_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ - writel(1 << AT91SAM9263_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} - -#ifdef CONFIG_HAS_DATAFLASH +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); @@ -128,14 +109,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); @@ -203,12 +184,12 @@ void at91_uhp_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer); + writel(1 << ATMEL_ID_CAN, &pmc->pcer); } #endif -- cgit v1.2.3 From c8e7ddd4c6d0e195fa2f28c534f5c8233547c59e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Wed, 9 Feb 2011 04:10:30 +0000 Subject: avr32: fix linking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes following error: ---8<--- avr32-linux-ld: --gc-sections and -r may not be used together --->8--- Since 8aba9dceebb14144e07d19593111ee3a999c37fc all avr32 boards are broken due to linking error as seen above. Signed-off-by: Andreas Bießmann --- arch/avr32/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 9488c49132..ef147105b7 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -26,4 +26,4 @@ CROSS_COMPILE ?= avr32-linux- CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax -PLATFORM_LDFLAGS += --relax +LDFLAGS_u-boot = --gc-sections --relax -- cgit v1.2.3 From 758472cc7b6cb8d8626f245f1607bad8b0ebda22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Mon, 18 Apr 2011 04:12:33 +0000 Subject: avr32/config.mk: simplify PLATFORM_RELFLAGS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes PLATFORM_RELFLAGS from board specific config.mk files and define them in arch specific config.mk file. Signed-off-by: Andreas Bießmann --- arch/avr32/config.mk | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index ef147105b7..a751a3d787 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -26,4 +26,6 @@ CROSS_COMPILE ?= avr32-linux- CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections + LDFLAGS_u-boot = --gc-sections --relax -- cgit v1.2.3 From bb7dc6af2031abb58434f583fe867b4cc966df5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Mon, 18 Apr 2011 04:12:34 +0000 Subject: avr32: use single linker script MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch move the atstk100x linker script to $(CPUDIR) and delete other pure copies of this file in each board directory. Signed-off-by: Andreas Bießmann --- arch/avr32/config.mk | 2 ++ arch/avr32/cpu/u-boot.lds | 72 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 arch/avr32/cpu/u-boot.lds (limited to 'arch') diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index a751a3d787..d8e7ebb0be 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -29,3 +29,5 @@ PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_u-boot = --gc-sections --relax + +LDSCRIPT = $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds new file mode 100644 index 0000000000..0e532f234e --- /dev/null +++ b/arch/avr32/cpu/u-boot.lds @@ -0,0 +1,72 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss (NOLOAD) : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + __bss_end__ = .; +} -- cgit v1.2.3 From 24890f11980eb70d835ca7e0b00d32284d8f546c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Tue, 12 Apr 2011 23:25:41 +0000 Subject: avr32: add ATAG_BOARDINFO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds a new ATAG_BORADINFO to U-Boot. This tag is intended to hand over the bd->bi_board_number to the linux kernel for early stage board information like a board revision or other kind of board specific decisions necessary before the linux peripherial drivers are up. Signed-off-by: Andreas Bießmann --- arch/avr32/include/asm/setup.h | 8 ++++++++ arch/avr32/lib/bootm.c | 11 +++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/avr32/include/asm/setup.h b/arch/avr32/include/asm/setup.h index e6ef8d6b50..7f5d883442 100644 --- a/arch/avr32/include/asm/setup.h +++ b/arch/avr32/include/asm/setup.h @@ -107,6 +107,13 @@ struct tag_ethernet { #define AETH_INVALID_PHY 0xff +/* board information information */ +#define ATAG_BOARDINFO 0x54410008 + +struct tag_boardinfo { + u32 board_number; +}; + struct tag { struct tag_header hdr; union { @@ -115,6 +122,7 @@ struct tag { struct tag_cmdline cmdline; struct tag_clock clock; struct tag_ethernet ethernet; + struct tag_boardinfo boardinfo; } u; }; diff --git a/arch/avr32/lib/bootm.c b/arch/avr32/lib/bootm.c index 8a47cfeb4a..c9a55ffb2c 100644 --- a/arch/avr32/lib/bootm.c +++ b/arch/avr32/lib/bootm.c @@ -165,6 +165,16 @@ static struct tag *setup_ethernet_tags(struct tag *params) return params; } +static struct tag *setup_boardinfo_tag(struct tag *params) +{ + params->hdr.tag = ATAG_BOARDINFO; + params->hdr.size = tag_size(tag_boardinfo); + + params->u.boardinfo.board_number = gd->bd->bi_board_number; + + return tag_next(params); +} + static void setup_end_tag(struct tag *params) { params->hdr.tag = ATAG_NONE; @@ -195,6 +205,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima params = setup_commandline_tag(params, commandline); params = setup_clock_tags(params); params = setup_ethernet_tags(params); + params = setup_boardinfo_tag(params); setup_end_tag(params); printf("\nStarting kernel at %p (params at %p)...\n\n", -- cgit v1.2.3