From 0ea76e92e989ce292f1eeadc0754b3ab9a50df16 Mon Sep 17 00:00:00 2001
From: Graeme Russ <graeme.russ@gmail.com>
Date: Sat, 12 Feb 2011 15:11:35 +1100
Subject: x86: Make cpu init functions weak

---
 arch/i386/cpu/cpu.c                 | 14 ++++++++++++--
 arch/i386/cpu/sc520/sc520.c         | 11 +++--------
 arch/i386/include/asm/u-boot-i386.h |  2 ++
 3 files changed, 17 insertions(+), 10 deletions(-)

(limited to 'arch')

diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c
index e96380aa92..2339cd41bb 100644
--- a/arch/i386/cpu/cpu.c
+++ b/arch/i386/cpu/cpu.c
@@ -87,7 +87,7 @@ static void reload_gdt(void)
 }
 
 
-int cpu_init_f(void)
+int x86_cpu_init_f(void)
 {
 	const u32 em_rst = ~X86_CR0_EM;
 	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
@@ -102,15 +102,25 @@ int cpu_init_f(void)
 
 	return 0;
 }
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
 
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
 {
+	const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+	/* turn on the cache and disable write through */
+	asm("movl	%%cr0, %%eax\n"
+	    "andl	%0, %%eax\n"
+	    "movl	%%eax, %%cr0\n"
+	    "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
 	reload_gdt();
 
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts ();
 	return 0;
 }
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 21037d29d7..b99408cc99 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ * Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -40,10 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
 
-void init_sc520(void)
+int cpu_init_f(void)
 {
-	const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
-
 	/*
 	 * Set the UARTxCTL register at it's slower,
 	 * baud clock giving us a 1.8432 MHz reference
@@ -85,10 +83,7 @@ void init_sc520(void)
 	/* turn on the SDRAM write buffer */
 	writeb(0x11, &sc520_mmcr->dbctl);
 
-	/* turn on the cache and disable write through */
-	asm("movl	%%cr0, %%eax\n"
-	    "andl	%0, %%eax\n"
-	    "movl	%%eax, %%cr0\n"  : : "i" (nw_cd_rst) : "eax");
+	return x86_cpu_init_f();
 }
 
 unsigned long init_sc520_dram(void)
diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h
index ce097a3bfa..80db52fc6f 100644
--- a/arch/i386/include/asm/u-boot-i386.h
+++ b/arch/i386/include/asm/u-boot-i386.h
@@ -25,7 +25,9 @@
 #define _U_BOOT_I386_H_	1
 
 /* cpu/.../cpu.c */
+int x86_cpu_init_r(void);
 int cpu_init_r(void);
+int x86_cpu_init_f(void);
 int cpu_init_f(void);
 
 /* cpu/.../timer.c */
-- 
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