From afabb498b749b48ca3ee7e833fe1501e2d6993cb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 12 Sep 2010 06:21:37 +0200 Subject: ppc4xx: Big header cleanup part 2, mostly PPC405 related This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/4xx_uart.c | 4 ++-- arch/powerpc/cpu/ppc4xx/cpu_init.c | 2 +- arch/powerpc/cpu/ppc4xx/gpio.c | 5 +++++ arch/powerpc/cpu/ppc4xx/speed.c | 2 +- 4 files changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index 9a11f3bad8d..5eaeefe8ead 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -312,10 +312,10 @@ static void serial_divs (int baudrate, unsigned long *pudiv, } *pudiv = udiv; - mfcpr(CPC0_PERD0, reg); + mfcpr(CPR0_PERD0, reg); reg &= ~0x0000ffff; reg |= ((udiv - 0) << 8) | (udiv - 0); - mtcpr(CPC0_PERD0, reg); + mtcpr(CPR0_PERD0, reg); *pbdiv = div / udiv; } #endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */ diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index 677a4b58966..d54b30e26f0 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -266,7 +266,7 @@ cpu_init_f (void) /* * Set EMAC noise filter bits */ - mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) diff --git a/arch/powerpc/cpu/ppc4xx/gpio.c b/arch/powerpc/cpu/ppc4xx/gpio.c index 1f9f93a696c..20f05722038 100644 --- a/arch/powerpc/cpu/ppc4xx/gpio.c +++ b/arch/powerpc/cpu/ppc4xx/gpio.c @@ -26,6 +26,9 @@ #include #include +/* Only compile this file for boards with GPIO support */ +#if defined(GPIO0_BASE) + #if defined(CONFIG_SYS_4xx_GPIO_TABLE) gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE; #endif @@ -252,4 +255,6 @@ void gpio_set_chip_configuration(void) } } } + +#endif /* GPIO0_BASE */ #endif /* CONFIG_SYS_4xx_GPIO_TABLE */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 4d7eb294ea8..abd4e910d23 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -902,7 +902,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read CPR_PRIMAD register */ - mfcpr(CPC0_PRIMAD, cpr_primad); + mfcpr(CPR0_PRIMAD, cpr_primad); /* * Determine PLB_DIV. -- cgit v1.2.3