From b1e41d1ceedf0fe90c7873bf9dfddd3690ccc11d Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 6 Jul 2017 10:33:21 +0200 Subject: powerpc, 8xx: Migrate to Kconfig Signed-off-by: Christophe Leroy Reviewed-by: Heiko Schocher --- arch/powerpc/cpu/mpc8xx/Kconfig | 148 +++++++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc8xx/fec.c | 8 +- 3 files changed, 153 insertions(+), 5 deletions(-) (limited to 'arch/powerpc/cpu/mpc8xx') diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index cb15dc5ebc..9e1ad33c28 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -10,6 +10,21 @@ choice endchoice +choice + prompt "CPU select" + default MPC866 + +config MPC866 + bool "MPC866" + +config MPC885 + bool "MPC885" + +endchoice + +config 8xx_GCLK_FREQ + int "CPU GCLK Frequency" + comment "Specific commands" config CMD_IMMAP @@ -19,4 +34,137 @@ config CMD_IMMAP siuinfo - print System Interface Unit (SIU) registers memcinfo - print Memory Controller registers + +comment "Configuration Registers" + +config SYS_SIUMCR + hex "SIUMCR register" + help + SIU Module Configuration (11-6) + +config SYS_SYPCR + hex "SYPCR register" + help + System Protection Control (11-9) + +config SYS_TBSCR + hex "TBSCR register" + help + Time Base Status and Control (11-26) + +config SYS_PISCR + hex "PISCR register" + help + Periodic Interrupt Status and Control (11-31) + +config SYS_PLPRCR_BOOL + bool "Customise PLPRCR" + +config SYS_PLPRCR + hex "PLPRCR register" + depends on SYS_PLPRCR_BOOL + help + PLL, Low-Power, and Reset Control Register (15-30) + +config SYS_SCCR + hex "SCCR register" + help + System Clock and reset Control Register (15-27) + +config SYS_SCCR_MASK + hex "MASK for setting SCCR register" + +config SYS_DER + hex "DER register" + help + Debug Event Register (37-47) + +comment "Memory mapping" + +config SYS_BR0_PRELIM + hex "Preliminary value for BR0" + +config SYS_OR0_PRELIM + hex "Preliminary value for OR0" + +config SYS_BR1_PRELIM_BOOL + bool "Define Bank 1" + +config SYS_BR1_PRELIM + hex "Preliminary value for BR1" + depends on SYS_BR1_PRELIM_BOOL + +config SYS_OR1_PRELIM + hex "Preliminary value for OR1" + depends on SYS_BR1_PRELIM_BOOL + +config SYS_BR2_PRELIM_BOOL + bool "Define Bank 2" + +config SYS_BR2_PRELIM + hex "Preliminary value for BR2" + depends on SYS_BR2_PRELIM_BOOL + +config SYS_OR2_PRELIM + hex "Preliminary value for OR2" + depends on SYS_BR2_PRELIM_BOOL + +config SYS_BR3_PRELIM_BOOL + bool "Define Bank 3" + +config SYS_BR3_PRELIM + hex "Preliminary value for BR3" + depends on SYS_BR3_PRELIM_BOOL + +config SYS_OR3_PRELIM + hex "Preliminary value for OR3" + depends on SYS_BR3_PRELIM_BOOL + +config SYS_BR4_PRELIM_BOOL + bool "Define Bank 4" + +config SYS_BR4_PRELIM + hex "Preliminary value for BR4" + depends on SYS_BR4_PRELIM_BOOL + +config SYS_OR4_PRELIM + hex "Preliminary value for OR4" + depends on SYS_BR4_PRELIM_BOOL + +config SYS_BR5_PRELIM_BOOL + bool "Define Bank 5" + +config SYS_BR5_PRELIM + hex "Preliminary value for BR5" + depends on SYS_BR5_PRELIM_BOOL + +config SYS_OR5_PRELIM + hex "Preliminary value for OR5" + depends on SYS_BR5_PRELIM_BOOL + +config SYS_BR6_PRELIM_BOOL + bool "Define Bank 6" + +config SYS_BR6_PRELIM + hex "Preliminary value for BR6" + depends on SYS_BR6_PRELIM_BOOL + +config SYS_OR6_PRELIM + hex "Preliminary value for OR6" + depends on SYS_BR6_PRELIM_BOOL + +config SYS_BR7_PRELIM_BOOL + bool "Define Bank 7" + +config SYS_BR7_PRELIM + hex "Preliminary value for BR7" + depends on SYS_BR7_PRELIM_BOOL + +config SYS_OR7_PRELIM + hex "Preliminary value for OR7" + depends on SYS_BR7_PRELIM_BOOL + +config SYS_IMMR + hex "Value for IMMR" + endmenu diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index b419edfd1e..16e7bf5fd5 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -48,7 +48,7 @@ void cpu_init_f(immap_t __iomem *immr) /* System integration timers. Don't change EBDF! (15-27) */ out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY); - clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK, + clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK, CONFIG_SYS_SCCR); /* diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index f2ea0d1b8a..56cb7a506e 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -376,7 +376,7 @@ static void fec_pin_init(int fecidx) out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed, ((bd->bi_intfreq + 4999999) / 5000000) << 1); -#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) +#if defined(CONFIG_MPC885) && defined(WANT_MII) /* use MDC for MII */ setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080); clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080); @@ -385,7 +385,7 @@ static void fec_pin_init(int fecidx) if (fecidx == 0) { #if defined(CONFIG_ETHER_ON_FEC1) -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ +#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */ #if !defined(CONFIG_RMII) @@ -435,7 +435,7 @@ static void fec_pin_init(int fecidx) } else if (fecidx == 1) { #if defined(CONFIG_ETHER_ON_FEC2) -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ +#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */ #if !defined(CONFIG_RMII) setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc); @@ -460,7 +460,7 @@ static void fec_pin_init(int fecidx) clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028); #endif /* CONFIG_RMII */ -#endif /* CONFIG_MPC885_FAMILY */ +#endif /* CONFIG_MPC885 */ #endif /* CONFIG_ETHER_ON_FEC2 */ } -- cgit v1.2.3