From b841b6e94662b3b21a56d6ecaab64dcdfb0d311c Mon Sep 17 00:00:00 2001 From: rick Date: Thu, 18 May 2017 14:37:53 +0800 Subject: nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick --- arch/nds32/include/asm/arch-ae3xx/ae3xx.h | 54 +++++++++++++++++++++++++ arch/nds32/include/asm/bootm.h | 65 +++++++++++++++++++++++++++++++ arch/nds32/include/asm/cache.h | 23 +++++++++-- arch/nds32/include/asm/mach-types.h | 1 + 4 files changed, 139 insertions(+), 4 deletions(-) create mode 100644 arch/nds32/include/asm/arch-ae3xx/ae3xx.h create mode 100644 arch/nds32/include/asm/bootm.h (limited to 'arch/nds32/include/asm') diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h new file mode 100644 index 00000000000..b074e8489a1 --- /dev/null +++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 Andes Technology Corporation + * Nobuhiro Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AE3XX_H +#define __AE3XX_H + +/* Hardware register bases */ + +/* Static Memory Controller (SRAM) */ +#define CONFIG_FTSMC020_BASE 0xe0400000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0xf0c00000 +/* AHB-to-APB Bridge */ +#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 +/* Reserved */ +#define CONFIG_RESERVED_01_BASE 0xe0500000 +/* Reserved */ +#define CONFIG_RESERVED_02_BASE 0xf0800000 +/* Reserved */ +#define CONFIG_RESERVED_03_BASE 0xf0900000 +/* Ethernet */ +#define CONFIG_FTMAC100_BASE 0xe0100000 +/* Reserved */ +#define CONFIG_RESERVED_04_BASE 0xf1000000 + +/* APB Device definitions */ + +/* UART1 */ +#define CONFIG_FTUART010_01_BASE 0xf0200000 +/* UART2 */ +#define CONFIG_FTUART010_02_BASE 0xf0300000 +/* Counter/Timers */ +#define CONFIG_FTTMR010_BASE 0xf0400000 +/* Watchdog Timer */ +#define CONFIG_FTWDT010_BASE 0xf0500000 +/* Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0xf0600000 +/* GPIO */ +#define CONFIG_FTGPIO010_BASE 0xf0700000 +/* I2C */ +#define CONFIG_FTIIC010_BASE 0xf0a00000 +/* SD Controller */ +#define CONFIG_FTSDC010_BASE 0xf0e00000 + +/* The following address was not defined in Linux */ + +/* Synchronous Serial Port Controller (SSP) 01 */ +#define CONFIG_FTSSP010_01_BASE 0xf0d00000 +#endif /* __AE3XX_H */ diff --git a/arch/nds32/include/asm/bootm.h b/arch/nds32/include/asm/bootm.h new file mode 100644 index 00000000000..6b10c078dfd --- /dev/null +++ b/arch/nds32/include/asm/bootm.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * SPDX-License-Identifier: GPL-2.0+ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef NDS32_BOOTM_H +#define NDS32_BOOTM_H + +extern void udc_disconnect(void); + +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +# define BOOTM_ENABLE_TAGS 1 +#else +# define BOOTM_ENABLE_TAGS 0 +#endif + +#ifdef CONFIG_SETUP_MEMORY_TAGS +# define BOOTM_ENABLE_MEMORY_TAGS 1 +#else +# define BOOTM_ENABLE_MEMORY_TAGS 0 +#endif + +#ifdef CONFIG_CMDLINE_TAG + #define BOOTM_ENABLE_CMDLINE_TAG 1 +#else + #define BOOTM_ENABLE_CMDLINE_TAG 0 +#endif + +#ifdef CONFIG_INITRD_TAG + #define BOOTM_ENABLE_INITRD_TAG 1 +#else + #define BOOTM_ENABLE_INITRD_TAG 0 +#endif + +#ifdef CONFIG_SERIAL_TAG + #define BOOTM_ENABLE_SERIAL_TAG 1 +void get_board_serial(struct tag_serialnr *serialnr); +#else + #define BOOTM_ENABLE_SERIAL_TAG 0 +static inline void get_board_serial(struct tag_serialnr *serialnr) +{ +} +#endif + +#ifdef CONFIG_REVISION_TAG + #define BOOTM_ENABLE_REVISION_TAG 1 +u32 get_board_rev(void); +#else + #define BOOTM_ENABLE_REVISION_TAG 0 +static inline u32 get_board_rev(void) +{ + return 0; +} +#endif + +#endif diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h index 9038821b48a..7e9aac80ff6 100644 --- a/arch/nds32/include/asm/cache.h +++ b/arch/nds32/include/asm/cache.h @@ -16,6 +16,7 @@ void icache_disable(void); int dcache_status(void); void dcache_enable(void); void dcache_disable(void); +void cache_flush(void); #define DEFINE_GET_SYS_REG(reg) \ static inline unsigned long GET_##reg(void) \ @@ -30,10 +31,24 @@ void dcache_disable(void); enum cache_t {ICACHE, DCACHE}; DEFINE_GET_SYS_REG(ICM_CFG); DEFINE_GET_SYS_REG(DCM_CFG); -#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ -#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) -#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ -#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) +/* I-cache sets (# of cache lines) per way */ +#define ICM_CFG_OFF_ISET 0 +/* I-cache ways */ +#define ICM_CFG_OFF_IWAY 3 +#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET) +#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY) +/* D-cache sets (# of cache lines) per way */ +#define DCM_CFG_OFF_DSET 0 +/* D-cache ways */ +#define DCM_CFG_OFF_DWAY 3 +#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET) +#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY) +/* I-cache line size */ +#define ICM_CFG_OFF_ISZ 6 +#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) +/* D-cache line size */ +#define DCM_CFG_OFF_DSZ 6 +#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) /* * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index 1959d7eb0bc..99904f9ed55 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -13,6 +13,7 @@ extern unsigned int __machine_arch_type; /* see arch/arm/kernel/arch.c for a description of these */ #define MACH_TYPE_ADPAG101P 1 +#define MACH_TYPE_ADPAE3XX 2 #ifdef CONFIG_ARCH_ADPAG101P # ifdef machine_arch_type -- cgit v1.2.3