From 16a18471bbdeb051d6905c1cba5a1bb84a2fbe49 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 24 Jun 2022 14:14:59 +0200 Subject: microblaze: Fix stack protection behavior When U-Boot starts stack protection can be already enabled that's why setup the lowest possible SLR value which is address 0. And the highest possible stack in front of U-Boot. That's why you should never load U-Boot to the beginning of DDR. There must be some space reserved. Code is using this location for early malloc space, early global data and stack. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/86b9748bad12142659804d6381bc6bbf20be44f1.1655299267.git.michal.simek@amd.com --- arch/microblaze/cpu/start.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/microblaze/cpu') diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 9e00eef1f4..715ef37b39 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -15,8 +15,9 @@ _start: mts rmsr, r0 /* disable cache */ - addi r8, r0, _end - mts rslr, r8 + mts rslr, r0 + addi r8, r0, _start + mts rshr, r8 #if defined(CONFIG_SPL_BUILD) addi r1, r0, CONFIG_SPL_STACK_ADDR -- cgit v1.2.3