From 8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 9 Dec 2016 12:29:13 +0200 Subject: arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock. Signed-off-by: Jyri Sarha Reviewed-by: Tom Rini --- arch/arm/mach-omap2/am33xx/ddr.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/mach-omap2/am33xx/ddr.c') diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 6acf30c5db0..690487e7c38 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -180,6 +180,10 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */ + if (regs->ocp_config) + writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config); } /** -- cgit v1.2.3