From b9a3c3a53a146883cda13c5f5869b0a8a07f9cb4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 20 Mar 2019 11:16:09 +0100 Subject: colibri-imx8qxp: fix ethernet functionality Fix Ethernet functionality. The FEC clock on i.MX 8X really has an additional by 2 divider plus our design requires the ENET0_RCLK50M_OUT on the ENET0_RGMII_TXC pin to be turned on for the Micrel PHY. Signed-off-by: Marcel Ziswiler --- arch/arm/mach-imx/imx8/clock.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/mach-imx/imx8/clock.c') diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index dff2d405fe6..53236c980e1 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -124,7 +124,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk) u32 imx_get_fecclk(void) { +#ifdef CONFIG_TARGET_COLIBRI_IMX8QXP + return mxc_get_clock(MXC_FEC_CLK)/2; +#else return mxc_get_clock(MXC_FEC_CLK); +#endif } static struct imx_i2c_map *get_i2c_desc(unsigned i2c_num) @@ -432,7 +436,11 @@ void init_clk_fec(int index) /* Configure GPR regisers */ sc_misc_set_control(ipc, enet[index], SC_C_TXCLK, 0); sc_misc_set_control(ipc, enet[index], SC_C_CLKDIV, 1); /* Enable divclk */ +#ifdef CONFIG_TARGET_COLIBRI_IMX8QXP + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 0); +#else sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 1); +#endif sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_125, 1); sc_misc_set_control(ipc, enet[index], SC_C_SEL_125, 0); sc_misc_set_control(ipc, enet[index], SC_C_IPG_STOP, 0); -- cgit v1.2.3