From 087bfe67ac2555c37b257335424b7c193d7f6afd Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 23 May 2019 11:05:45 +0800 Subject: armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu Signed-off-by: Yinbo Zhu Reviewed-by: Prabhakar Kushwaha --- arch/arm/include/asm/arch-fsl-layerscape/clock.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index cf058d22a9..b37a08d265 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP Semiconductors * */ @@ -14,6 +15,7 @@ enum mxc_clock { MXC_BUS_CLK, MXC_UART_CLK, MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; -- cgit v1.2.3