From e11c6c279d823dc0d2f470c5c2e3c0a9854a640f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Feb 2015 10:47:28 -0700 Subject: arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass Acked-by: Siarhei Siamashka Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/system.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/include/asm/system.h') diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 89f22946895..7820486df00 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -142,6 +142,21 @@ void flush_l3_cache(void); #ifndef __ASSEMBLY__ +/** + * save_boot_params() - Save boot parameters before starting reset sequence + * + * If you provide this function it will be called immediately U-Boot starts, + * both for SPL and U-Boot proper. + * + * All registers are unchanged from U-Boot entry. No registers need be + * preserved. + * + * This is not a normal C function. There is no stack. Return by branching to + * save_boot_params_ret. + * + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); + */ + #define isb() __asm__ __volatile__ ("" : : : "memory") #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); -- cgit v1.2.3 From dcd468b8f43c5077c42c75b15cf3204e6b6be46c Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:42 -0800 Subject: armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun --- arch/arm/include/asm/system.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/system.h') diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7820486df00..2a5bed2e46b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -70,6 +70,7 @@ void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); +int __asm_flush_l3_cache(void); void armv8_switch_to_el2(void); void armv8_switch_to_el1(void); -- cgit v1.2.3