From a922d0d102750f287283e33cf364c37f79e1a361 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Fri, 15 Nov 2019 11:04:45 +0800 Subject: ram: rk3399: migrate to use common code For there are some structures and functions are common for all rockchip SoCs, migrate to use the common code so that we can clean up reduandent codes. Signed-off-by: YouMin Chen Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 88 +++++++++-------------- 1 file changed, 32 insertions(+), 56 deletions(-) (limited to 'arch/arm/include/asm/arch-rockchip') diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 485bb3d8896..f0a664478f6 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -6,6 +6,7 @@ #ifndef _ASM_ARCH_SDRAM_RK3399_H #define _ASM_ARCH_SDRAM_RK3399_H #include +#include struct rk3399_ddr_pctl_regs { u32 denali_ctl[332]; @@ -19,55 +20,6 @@ struct rk3399_ddr_pi_regs { u32 denali_pi[200]; }; -union noc_ddrtimingc0 { - u32 d32; - struct { - unsigned burstpenalty : 4; - unsigned reserved0 : 4; - unsigned wrtomwr : 6; - unsigned reserved1 : 18; - } b; -}; - -union noc_ddrmode { - u32 d32; - struct { - unsigned autoprecharge : 1; - unsigned bypassfiltering : 1; - unsigned fawbank : 1; - unsigned burstsize : 2; - unsigned mwrsize : 2; - unsigned reserved2 : 1; - unsigned forceorder : 8; - unsigned forceorderstate : 8; - unsigned reserved3 : 8; - } b; -}; - -struct rk3399_msch_regs { - u32 coreid; - u32 revisionid; - u32 ddrconf; - u32 ddrsize; - u32 ddrtiminga0; - u32 ddrtimingb0; - u32 ddrtimingc0; - u32 devtodev0; - u32 reserved0[(0x110 - 0x20) / 4]; - u32 ddrmode; - u32 reserved1[(0x1000 - 0x114) / 4]; - u32 agingx0; -}; - -struct rk3399_msch_timings { - u32 ddrtiminga0; - u32 ddrtimingb0; - union noc_ddrtimingc0 ddrtimingc0; - u32 devtodev0; - union noc_ddrmode ddrmode; - u32 agingx0; -}; - struct rk3399_ddr_cic_regs { u32 cic_ctrl0; u32 cic_ctrl1; @@ -84,14 +36,38 @@ struct rk3399_ddr_cic_regs { #define START 1 /* DENALI_CTL_68 */ -#define PWRUP_SREFRESH_EXIT (1 << 16) +#define PWRUP_SREFRESH_EXIT BIT(16) /* DENALI_CTL_274 */ #define MEM_RST_VALID 1 +struct msch_regs { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrsize; + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + u32 reserved0[(0x110 - 0x20) / 4]; + union noc_ddrmode ddrmode; + u32 reserved1[(0x1000 - 0x114) / 4]; + u32 agingx0; +}; + +struct sdram_msch_timings { + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + union noc_ddrmode ddrmode; + u32 agingx0; +}; + struct rk3399_sdram_channel { struct sdram_cap_info cap_info; - struct rk3399_msch_timings noc_timings; + struct sdram_msch_timings noc_timings; }; struct rk3399_sdram_params { @@ -102,11 +78,11 @@ struct rk3399_sdram_params { struct rk3399_ddr_publ_regs phy_regs; }; -#define PI_CA_TRAINING (1 << 0) -#define PI_WRITE_LEVELING (1 << 1) -#define PI_READ_GATE_TRAINING (1 << 2) -#define PI_READ_LEVELING (1 << 3) -#define PI_WDQ_LEVELING (1 << 4) +#define PI_CA_TRAINING BIT(0) +#define PI_WRITE_LEVELING BIT(1) +#define PI_READ_GATE_TRAINING BIT(2) +#define PI_READ_LEVELING BIT(3) +#define PI_WDQ_LEVELING BIT(4) #define PI_FULL_TRAINING 0xff #endif -- cgit v1.2.3