From 0ea3671d35dc5a6f2555bb5307d76e229e81f47d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Thu, 29 Sep 2016 12:42:44 +0800 Subject: armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang [York Sun: Reformatted commit message] Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 3d00909b2cf..d88543d0634 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -168,6 +168,8 @@ struct sys_info { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) /* Device Configuration and Pin Control */ +#define DCFG_DCSR_PORCR1 0x0 + struct ccsr_gur { u32 porsr1; /* POR status 1 */ #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 -- cgit v1.2.3