From fb072a3ead8cc9f4a5e236a4b424e4df16f5e5ef Mon Sep 17 00:00:00 2001 From: Chandan Nath Date: Mon, 9 Jan 2012 20:38:56 +0000 Subject: ARM:AM33XX: Fix ddr and timer register offset This patch is added to update incorrect ddr and timer register offset. Signed-off-by: Chandan Nath Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/include/asm/arch-am33xx/ddr_defs.h') diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 9638b4caa3..ba6b59b89f 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -76,7 +76,7 @@ struct emif_regs { unsigned int sdrmcsr; /* offset 0x3C */ unsigned int res2[8]; unsigned int sdritr; /* offset 0x60 */ - unsigned int res3[20]; + unsigned int res3[32]; unsigned int ddrphycr; /* offset 0xE4 */ unsigned int ddrphycsr; /* offset 0xE8 */ unsigned int ddrphycr2; /* offset 0xEC */ @@ -161,10 +161,10 @@ struct ddr_regs { unsigned int dt0wiratio1; /* offset 0x0F4 */ unsigned int dt0giratio0; /* offset 0x0FC */ unsigned int dt0giratio1; /* offset 0x100 */ - unsigned int resv6[2]; + unsigned int resv6[1]; unsigned int dt0fwsratio0; /* offset 0x108 */ unsigned int dt0fwsratio1; /* offset 0x10C */ - unsigned int resv7[5]; + unsigned int resv7[4]; unsigned int dt0wrsratio0; /* offset 0x120 */ unsigned int dt0wrsratio1; /* offset 0x124 */ unsigned int resv8[3]; -- cgit v1.2.3