From 000820b5835c2b8b863af992b66dc973dc4bd202 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Thu, 8 Mar 2012 17:15:47 +0530 Subject: am335x: Enable RTC 32K OSC clock In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/include/asm/arch-am33xx/cpu.h') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 6cfbef76a7..819fd2f026 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -169,6 +169,12 @@ struct cm_dpll { unsigned int clktimer2clk; /* offset 0x08 */ }; +/* Control Module RTC registers */ +struct cm_rtc { + unsigned int rtcclkctrl; /* offset 0x0 */ + unsigned int clkstctrl; /* offset 0x4 */ +}; + /* Watchdog timer registers */ struct wd_timer { unsigned int resv1[4]; @@ -218,6 +224,15 @@ struct gptimer { unsigned int tcar2; /* offset 0x58 */ }; +/* RTC Registers */ +struct rtc_regs { + unsigned int res[21]; + unsigned int osc; /* offset 0x54 */ + unsigned int res2[5]; + unsigned int kick0r; /* offset 0x6c */ + unsigned int kick1r; /* offset 0x70 */ +}; + /* UART Registers */ struct uart_sys { unsigned int resv1[21]; -- cgit v1.2.3