From bc0f4ed133e9996d00349b6b82ba65126fd70514 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 5 Jun 2018 15:18:32 +0530 Subject: arm64: zynqmp: Split emmc configuration into emmc0 and emmc1 This patch splits the current mini emmc configuration into emmc0 and emmc1 configurations because emmc is probed at boot time and on systems which have only one interface mini configuration is failing on unused interface. This patch also adds required clock node in dts and enables CONFIG_MMC_SDHCI_ZYNQ through defconfig. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/zynqmp-mini-emmc.dts | 75 -------------------------------------- arch/arm/dts/zynqmp-mini-emmc0.dts | 67 ++++++++++++++++++++++++++++++++++ arch/arm/dts/zynqmp-mini-emmc1.dts | 67 ++++++++++++++++++++++++++++++++++ 4 files changed, 136 insertions(+), 76 deletions(-) delete mode 100644 arch/arm/dts/zynqmp-mini-emmc.dts create mode 100644 arch/arm/dts/zynqmp-mini-emmc0.dts create mode 100644 arch/arm/dts/zynqmp-mini-emmc1.dts (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 078c21b4010..493652ea8c4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -147,7 +147,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zturn.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ - zynqmp-mini-emmc.dtb \ + zynqmp-mini-emmc0.dtb \ + zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-mini-emmc.dts b/arch/arm/dts/zynqmp-mini-emmc.dts deleted file mode 100644 index e5b3c5fc78c..00000000000 --- a/arch/arm/dts/zynqmp-mini-emmc.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP Mini Configuration - * - * (C) Copyright 2018, Xilinx, Inc. - * - * Siva Durga Prasad - */ - -/dts-v1/; - -/ { - model = "ZynqMP MINI EMMC"; - compatible = "xlnx,zynqmp"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &dcc; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x20000000>; - }; - - dcc: dcc { - compatible = "arm,dcc"; - status = "disabled"; - u-boot,dm-pre-reloc; - }; - - amba: amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - sdhci0: sdhci@ff160000 { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - reg = <0x0 0xff160000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <0>; - }; - - sdhci1: sdhci@ff170000 { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - reg = <0x0 0xff170000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <1>; - }; - }; -}; - -&dcc { - status = "okay"; -}; - -&sdhci0 { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; -}; diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts new file mode 100644 index 00000000000..24dd1ab9df0 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP Mini Configuration + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Siva Durga Prasad + */ + +/dts-v1/; + +/ { + model = "ZynqMP MINI EMMC"; + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdhci0: sdhci@ff160000 { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0x0 0xff160000 0x0 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + xlnx,device_id = <0>; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts new file mode 100644 index 00000000000..d1549b6dc6d --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP Mini Configuration + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Siva Durga Prasad + */ + +/dts-v1/; + +/ { + model = "ZynqMP MINI EMMC"; + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdhci1: sdhci@ff170000 { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0x0 0xff170000 0x0 0x1000>; + clock-names = "clk_xin", "clk_xin"; + xlnx,device_id = <1>; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; -- cgit v1.2.3