From add73a1dad49236fd1f5b2ebaca87bed36db247d Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:11 +0800 Subject: arm: ls1021a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/dts/ls1021a.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 37be16905b9..c40d87cdf8c 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -374,5 +374,36 @@ interrupts = ; dr_mode = "host"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x03400000 0x20000 /* dbi registers */ + 0x01570000 0x10000 /* pf controls registers */ + 0x24000000 0x20000>; /* configuration space */ + reg-names = "dbi", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x03500000 0x10000 /* dbi registers */ + 0x01570000 0x10000 /* pf controls registers */ + 0x34000000 0x20000>; /* configuration space */ + reg-names = "dbi", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v1.2.3 From 048a04530700704af622dc80a192b59de2e65fa2 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:12 +0800 Subject: arm: ls1012a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1012a.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 024527e815f..c4ca9c12cba 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -103,5 +103,20 @@ status = "disabled"; }; + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x40 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v1.2.3 From ed9bddefb904c3d46bb0dd2e06bcfb082c666579 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:13 +0800 Subject: armv8: ls1043a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1043a.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index f038f96171e..fe6698f1612 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -236,5 +236,51 @@ interrupts = <0 63 0x4>; dr_mode = "host"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */ + 0x00 0x03410000 0x0 0x10000 /* lut registers */ + 0x40 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */ + 0x00 0x03510000 0x0 0x10000 /* lut registers */ + 0x48 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3600000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */ + 0x00 0x03610000 0x0 0x10000 /* lut registers */ + 0x50 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v1.2.3 From b948a16f3439b7bc4fed0adfc465a5634103e970 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:14 +0800 Subject: armv8: ls1046a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1046a.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 359a9d13bf8..aaf0ae90fdb 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -216,5 +216,54 @@ big-endian; status = "disabled"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x40 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ + 0x00 0x03580000 0x0 0x40000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x48 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3600000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ + 0x00 0x03680000 0x0 0x40000 /* lut registers */ + 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ + 0x50 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v1.2.3 From 33f61e07b3d020f708899304e43f6fd7301198b8 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:15 +0800 Subject: armv8: ls2080a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/dts/fsl-ls2080a.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index f76e981c54f..79047d502ba 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -89,4 +89,64 @@ interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x80000 /* lut registers */ + 0x10 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ + 0x00 0x03580000 0x0 0x80000 /* lut registers */ + 0x12 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3600000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ + 0x00 0x03680000 0x0 0x80000 /* lut registers */ + 0x14 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3700000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */ + 0x00 0x03780000 0x0 0x80000 /* lut registers */ + 0x16 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; -- cgit v1.2.3 From a73058740df230daddce7e1956d1051b5171783d Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Tue, 27 Dec 2016 10:24:44 +0800 Subject: armv8: ls1012: added usb nodes in dts The LS1012A processor has two integrated USB controllers. One is USB2.0 controller, the other is USB3.0 controller that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1012a.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index c4ca9c12cba..f8665b6e0ca 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -118,5 +118,20 @@ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + usb0: usb2@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x0 0x8600000 0x0 0x1000>; + interrupts = <0 139 0x4>; + dr_mode = "host"; + fsl,usb-erratum-a005697; + }; + + usb1: usb3@2f00000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + }; }; }; -- cgit v1.2.3 From e1f39751d533a9d2bc439f8ec72683e6405b5e8e Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 7 Dec 2016 11:54:32 +0800 Subject: armv8: ls1012a: add eSDHC nodes This patch is to add eSDHC nodes for ls1012a. Signed-off-by: Yangbo Lu Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1012a.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index f8665b6e0ca..ed5ea54a5ec 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -54,6 +54,22 @@ status = "disabled"; }; + esdhc0: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + big-endian; + bus-width = <4>; + }; + + esdhc1: esdhc@1580000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1580000 0x0 0x10000>; + interrupts = <0 65 0x4>; + big-endian; + non-removable; + bus-width = <4>; + }; i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; -- cgit v1.2.3