From b647442ce8a3c191677155ff29ca0c41dc8c6d0c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 17:17:51 +0800 Subject: rockchip: rk322x: add dts file The dts files are from kernel and with modify to adapt U-Boot. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/dts/rk3229-evb.dts | 77 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/arm/dts/rk3229-evb.dts (limited to 'arch/arm/dts/rk3229-evb.dts') diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts new file mode 100644 index 00000000000..ccdac1c79a9 --- /dev/null +++ b/arch/arm/dts/rk3229-evb.dts @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +#include "rk322x.dtsi" + +/ { + model = "Rockchip RK3229 Evaluation board"; + compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + + chosen { + stdout-path = &uart2; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + ext_gmac: ext_gmac { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&dmc { + rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>; + rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 + 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 + 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 + 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4 + 0x0 0x924>; + rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>; + rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15 + 0 300 3 0 120>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&emmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- cgit v1.2.3