From 62c04970e29fca9188f6c23f514bf42d93f7aebd Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 16 May 2023 16:23:39 +0530 Subject: arm: dts: k3-j721s2-*-common-proc-board: Add USB support The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju Signed-off-by: Ravi Gunasekaran --- arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi') diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 12a444820ca..48a9e3c5acc 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -99,6 +99,10 @@ bootph-pre-ram; }; +&main_usbss0_pins_default { + bootph-pre-ram; +}; + &wkup_pmx0 { bootph-pre-ram; }; @@ -127,6 +131,15 @@ bootph-pre-ram; }; +&usbss0 { + bootph-pre-ram; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-pre-ram; +}; + &mcu_cpsw { reg = <0x0 0x46000000 0x0 0x200000>, <0x0 0x40f00200 0x0 0x8>; @@ -144,6 +157,10 @@ u-boot,mux-autoprobe; }; +&usb_serdes_mux { + u-boot,mux-autoprobe; +}; + &main_sdhci0 { bootph-pre-ram; }; -- cgit v1.2.3