From 4c6bd44936e39f2409b996baf2bbb592d905ca08 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 18 Apr 2020 07:13:41 -0700 Subject: MLK-23574-32 DTS: imx8mn: Update DDR4 EVK DTS and binding files Sync the DTS and binding files with v5.10.y kernel. Some updates in u-boot: 1. Add alias for flexspi, usbotg1 and usbotg2. 2. Add usbotg2 nodes 3. Add i2c force idle pins 4. Update usbotg nodes to use excon 5. Add pmic and i2c to -u-boot.dtsi for SPL DM Signed-off-by: Ye Li (cherry picked from commit 32cdd89a0e06bf40f8240cb7063c142321a16200) (cherry picked from commit 37c4bddfc887cd5fb5f64846d97722ae3705cb42) (cherry picked from commit 208527da22770ac3749afc589763087c9ca6e43d) --- arch/arm/dts/imx8mn.dtsi | 546 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 411 insertions(+), 135 deletions(-) (limited to 'arch/arm/dts/imx8mn.dtsi') diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index edcb415b53..6abbb3d992 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -4,10 +4,9 @@ */ #include -#include -#include #include #include +#include #include #include @@ -36,9 +35,9 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; + spi0 = &flexspi; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { @@ -146,6 +145,21 @@ }; }; + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -188,11 +202,76 @@ clock-output-names = "clk_ext4"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MN_DRAM_PLL_OUT>, <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>, <&clk IMX8MN_CLK_DRAM_APB>, + <&clk IMX8MN_CLK_DRAM_CORE>, <&clk IMX8MN_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>, + <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>, + <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>, + <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIOMIX */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <0>; + #power-domain-cells = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + }; + + usb_otg1_pd: usbotg1-pd{ + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU2D&3D */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <4>; + #power-domain-cells = <0>; + domain-name = "gpumix"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + }; + + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <9>; + #power-domain-cells = <0>; + domain-name = "dispmix"; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <10>; + #power-domain-cells = <0>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; psci { @@ -200,7 +279,7 @@ method = "smc"; }; - thermal-zones { + thermal: thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; @@ -242,14 +321,60 @@ arm,no-tick-in-suspend; }; + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; + }; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_DSI_CLKREF_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_DSI_PCLK_RESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MN_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; + }; + }; soc@0 { - compatible = "fsl,imx8mn-soc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; nvmem-cells = <&imx8mn_uid>; nvmem-cell-names = "soc_unique_id"; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -257,7 +382,7 @@ #size-cells = <1>; ranges; - spba: spba-bus@30000000 { + spba2: spba-bus@30000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -497,7 +622,7 @@ }; sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302b0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, @@ -508,7 +633,7 @@ }; sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, @@ -529,7 +654,7 @@ }; ocotp: efuse@30350000 { - compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; + compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon", "simple-mfd"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; #address-cells = <1>; @@ -546,6 +671,12 @@ fec_mac_address: mac-address@90 { reg = <0x90 6>; }; + + imx8mn_soc: imx8mn-soc { + compatible = "fsl,imx8mn-soc"; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; + }; }; anatop: anatop@30360000 { @@ -554,6 +685,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -614,54 +761,6 @@ interrupts = ; #reset-cells = <1>; }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx8mn-gpc"; - reg = <0x303a0000 0x10000>; - interrupt-parent = <&gic>; - interrupts = ; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_hsiomix: power-domain@0 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MN_CLK_USB_BUS>; - }; - - pgc_otg1: power-domain@1 { - #power-domain-cells = <0>; - reg = ; - power-domains = <&pgc_hsiomix>; - }; - - pgc_gpumix: power-domain@2 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, - <&clk IMX8MN_CLK_GPU_SHADER_DIV>, - <&clk IMX8MN_CLK_GPU_BUS_ROOT>, - <&clk IMX8MN_CLK_GPU_AHB>; - resets = <&src IMX8MQ_RESET_GPU_RESET>; - }; - - dispmix_pd: power-domain@3 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, - <&clk IMX8MN_CLK_DISP_AXI_ROOT>, - <&clk IMX8MN_CLK_DISP_APB_ROOT>; - }; - - mipi_pd: power-domain@4 { - #power-domain-cells = <0>; - reg = ; - power-domains = <&dispmix_pd>; - }; - }; - }; }; aips2: bus@30400000 { @@ -731,80 +830,88 @@ #size-cells = <1>; ranges; - ecspi1: spi@30820000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + spba1: spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, - <&clk IMX8MN_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; - ecspi2: spi@30830000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, - <&clk IMX8MN_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi1: spi@30820000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, + <&clk IMX8MN_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi3: spi@30840000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, - <&clk IMX8MN_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, + <&clk IMX8MN_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART1_ROOT>, - <&clk IMX8MN_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, + <&clk IMX8MN_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART3_ROOT>, - <&clk IMX8MN_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_UART1_ROOT>, + <&clk IMX8MN_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART2_ROOT>, - <&clk IMX8MN_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; + uart3: serial@30880000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_UART3_ROOT>, + <&clk IMX8MN_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_UART2_ROOT>, + <&clk IMX8MN_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; }; crypto: crypto@30900000 { @@ -894,6 +1001,7 @@ reg = <0x30aa0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_MU_ROOT>; + clock-names = "mu"; #mbox-cells = <2>; }; @@ -948,12 +1056,15 @@ interrupts = ; clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, <&clk IMX8MN_CLK_QSPI_ROOT>; - clock-names = "fspi", "fspi_en"; + clock-names = "fspi_en", "fspi"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; status = "disabled"; }; sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, @@ -964,7 +1075,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , @@ -992,6 +1103,7 @@ nvmem-cell-names = "mac-address"; nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; @@ -1004,17 +1116,82 @@ #size-cells = <1>; ranges; + lcdif: lcd-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, + <500000000>, + <200000000>; + interrupts = ; + resets = <&lcdif_resets>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi_controller@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, + <594000000>; + interrupts = ; + resets = <&mipi_dsi_resets>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, + <&clk IMX8MN_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, + <&clk IMX8MN_SYS_PLL1_100M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&usb_otg1_pd>; status = "disabled"; }; @@ -1023,6 +1200,28 @@ #index-cells = <1>; reg = <0x32e40200 0x200>; }; + + usbotg2: usb@32e50000 { + compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x32e50000 0x200>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, + <&clk IMX8MN_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, + <&clk IMX8MN_SYS_PLL1_100M>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@32e50200 { + compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x32e50200 0x200>; + }; + }; dma_apbh: dma-controller@33000000 { @@ -1080,6 +1279,38 @@ }; }; + gpu: gpu@38000000 { + compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x38000000 0x0 0x40000>, + <0x0 0x40000000 0x0 0x80000000>, + <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <600000000>, <600000000>; + power-domains = <&gpumix_pd>; + status = "disabled"; + }; + usbphynop1: usbphynop1 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -1088,4 +1319,49 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + + dispmix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mn-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mn-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mn-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + }; }; -- cgit v1.2.3