From aef654a2ed386d8bd53053383f6bf15ba016a79c Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Tue, 30 Jul 2019 17:29:57 +0300 Subject: armv8: fsl-layerscape: make icid setup endianness aware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index b1a950e7f9..82c5a8b123 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -17,7 +17,10 @@ static void set_icid(struct icid_id_table *tbl, int size) int i; for (i = 0; i < size; i++) - out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); + if (tbl[i].le) + out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg); + else + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); } #ifdef CONFIG_SYS_DPAA_FMAN -- cgit v1.2.3