From c8d9ceaf061c5ea5c17ee9e95dbff563e41904c0 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 2 Apr 2012 06:18:49 +0000 Subject: ARM: 926ejs: use debug() for misaligned addresses Misaligned warnings are useful to debug faulty drivers. A misaligned warning is printed also when the driver is correct - use debug() instead of printf(). Signed-off-by: Stefano Babic CC: Albert Aribaud CC: Mike Frysinger CC: Marek Vasut Acked-by: Marek Vasut --- arch/arm/cpu/arm926ejs/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/arm926ejs/cache.c') diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 5b23e3a71b..4430578a81 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -55,7 +55,7 @@ static int check_cache_range(unsigned long start, unsigned long stop) ok = 0; if (!ok) - printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", start, stop); return ok; -- cgit v1.2.3 From c6201553ba73616eed0f416f66d28c39691692bd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 6 Apr 2012 03:25:06 +0000 Subject: ARM926EJS: Make asm routines volatile in cache ops We certainly don't want the compiler to reorganise the code for dcache flushing. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Albert ARIBAUD Acked-by: Mike Frysinger Acked-by: Stefano Babic --- arch/arm/cpu/arm926ejs/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/arm926ejs/cache.c') diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 4430578a81..07f036f18b 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -82,7 +82,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) start += CONFIG_SYS_CACHELINE_SIZE; } - asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); } void flush_cache(unsigned long start, unsigned long size) -- cgit v1.2.3 From 2694bb9bcc8ca9636faf38c866dda7bf0529e35f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 6 Apr 2012 03:25:07 +0000 Subject: ARM926EJS: Fix cache.c to comply with checkpatch.pl Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Albert ARIBAUD --- arch/arm/cpu/arm926ejs/cache.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'arch/arm/cpu/arm926ejs/cache.c') diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 07f036f18b..2740ad7e29 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -30,7 +30,7 @@ void invalidate_dcache_all(void) { - asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); } void flush_dcache_all(void) @@ -40,7 +40,7 @@ void flush_dcache_all(void) "mrc p15, 0, r15, c7, c14, 3\n" "bne 0b\n" "mcr p15, 0, %0, c7, c10, 4\n" - ::"r"(0):"memory" + : : "r"(0) : "memory" ); } @@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; } } @@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; } - asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); } void flush_cache(unsigned long start, unsigned long size) @@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size) /* * Stub implementations for l2 cache operations */ -void __l2_cache_disable(void) -{ -} +void __l2_cache_disable(void) {} + void l2_cache_disable(void) - __attribute__((weak, alias("__l2_cache_disable"))); + __attribute__((weak, alias("__l2_cache_disable"))); -- cgit v1.2.3