From f83ed441a941d5890da20e8cf00a574af49fe46c Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Tue, 8 Mar 2011 03:07:31 +0000 Subject: armv7: cache maintenance operations for armv7 - Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V --- README | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README') diff --git a/README b/README index 446966dc16..4f371600ef 100644 --- a/README +++ b/README @@ -460,6 +460,11 @@ The following options need to be configured: Note: If a "bootargs" environment is defined, it will overwride the defaults discussed just above. +- Cache Configuration: + CONFIG_SYS_NO_ICACHE - Do not enable instruction cache in U-Boot + CONFIG_SYS_NO_DCACHE - Do not enable data cache in U-Boot + CONFIG_SYS_NO_L2CACHE- Do not enable L2 cache in U-Boot + - Serial Ports: CONFIG_PL010_SERIAL -- cgit v1.2.3