From 3fa48f0a1afb5f9eae5e8a701b836befb98649db Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Fri, 13 Apr 2018 00:18:22 +0530 Subject: board: freescale: ls1012ardb: Add command to switch QSPI bank Add command "boot_bank X" to switch the boot bank to either 1 or 2. Signed-off-by: Jagdish Gediya Reviewed-by: York Sun --- board/freescale/ls1012ardb/ls1012ardb.c | 85 +++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index a1668b97284..888f8500d4b 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -25,6 +25,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define BOOT_FROM_UPPER_BANK 0x2 +#define BOOT_FROM_LOWER_BANK 0x1 + int checkboard(void) { #ifdef CONFIG_TARGET_LS1012ARDB @@ -211,3 +214,85 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +static int switch_to_bank1(void) +{ + u8 data; + int ret; + + i2c_set_bus_num(0); + + data = 0xf4; + ret = i2c_write(0x24, 0x3, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x3, data); + } + + return ret; +} + +static int switch_to_bank2(void) +{ + u8 data; + int ret; + + i2c_set_bus_num(0); + + data = 0xfc; + ret = i2c_write(0x24, 0x7, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x7, data); + goto err; + } + + data = 0xf5; + ret = i2c_write(0x24, 0x3, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x3, data); + } +err: + return ret; +} + +static int convert_flash_bank(int bank) +{ + int ret = 0; + + switch (bank) { + case BOOT_FROM_UPPER_BANK: + ret = switch_to_bank2(); + break; + case BOOT_FROM_LOWER_BANK: + ret = switch_to_bank1(); + break; + default: + ret = CMD_RET_USAGE; + break; + }; + + return ret; +} + +static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else if (strcmp(argv[1], "2") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)" +); -- cgit v1.2.3 From e784cf1bf2a1fca2667198eea0d8031ae0ceeaf3 Mon Sep 17 00:00:00 2001 From: Brendan Shanks Date: Mon, 16 Jul 2018 13:28:24 -0700 Subject: arm: ls102xa: Fix RGMII phy-connection-type FDT fixup In ft_fixup_enet_phy_connect_type(), use strlen() instead of sizeof() on the pointer result of phy_string_for_interface(). sizeof() was returning the size of the pointer (4 bytes), resulting in the phy-connection-type being set to "rgmi" rather than "rgmii-id". Signed-off-by: Brendan Shanks Cc: York Sun Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/fdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 6c3caf84b20..8bf9c42b226 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -64,8 +64,8 @@ void ft_fixup_enet_phy_connect_type(void *fdt) do_fixup_by_path(fdt, enet_path, "phy-connection-type", phy_string_for_interface( PHY_INTERFACE_MODE_RGMII_ID), - sizeof(phy_string_for_interface( - PHY_INTERFACE_MODE_RGMII_ID)), + strlen(phy_string_for_interface( + PHY_INTERFACE_MODE_RGMII_ID)) + 1, 1); } } -- cgit v1.2.3 From b2486b40dce98ca26bcb6e1dda69efb1b0443b9a Mon Sep 17 00:00:00 2001 From: Vinitha V Pillai Date: Tue, 17 Jul 2018 11:52:45 +0530 Subject: Board: ls1088ardb: Enable PCIe config for Secure boot defconfigs Signed-off-by: Vinitha V Pillai Reviewed-by: York Sun --- configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 59356095cd2..08b9caeb34d 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -48,6 +48,10 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y -- cgit v1.2.3 From 6ce83fb3d6ac1cd25772b3c8c1265afbfa42f718 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Tue, 12 Sep 2017 19:56:41 +0200 Subject: FSL PCI: Configure PCIe reference ratio Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured. This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform. Signed-off-by: Joakim Tjernlund Reviewed-by: York Sun --- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 375b8549c59..b4c85566861 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -321,6 +321,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pci_setup_indirect(hose, cfg_addr, cfg_data); +#ifdef PEX_CCB_DIV + /* Configure the PCIE controller core clock ratio */ + pci_hose_write_config_dword(hose, dev, 0x440, + ((gd->bus_clk / 1000000) * + (16 / PEX_CCB_DIV)) / 333); +#endif block_rev = in_be32(&pci->block_rev1); if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2]; /* 0xDC0 */ -- cgit v1.2.3 From c022ec039d3f32a153a1f7d3b1ffe3dd548d9be4 Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Thu, 2 Aug 2018 16:31:28 +0530 Subject: fsl/mc: Limit the ethernet name to ETH_NAME_LEN The ethernet name should be within the ETH_NAME_LEN, as this is the buffer space allocated to ethernet name. Otherwise, this causes buffer overflow. Reported-by: Ioana Ciornei Signed-off-by: Pankaj Bansal Reviewed-by: York Sun --- drivers/net/fsl-mc/mc.c | 6 +++--- drivers/net/ldpaa_eth/ldpaa_eth.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 982024e31ea..940025a4673 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -322,7 +322,7 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type) { int i, err = 0, ret = 0; - char ethname[10]; + char ethname[ETH_NAME_LEN]; struct eth_device *eth_dev; for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { @@ -331,8 +331,8 @@ static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type) (wriop_get_phy_address(i) == -1)) continue; - sprintf(ethname, "DPMAC%d@%s", i, - phy_interface_strings[wriop_get_enet_if(i)]); + snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i, + phy_interface_strings[wriop_get_enet_if(i)]); eth_dev = eth_get_dev_by_name(ethname); if (eth_dev == NULL) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 79facb4a445..a25b7cd9067 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -993,8 +993,8 @@ static int ldpaa_eth_netdev_init(struct eth_device *net_dev, int err; struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; - sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id, - phy_interface_strings[enet_if]); + snprintf(net_dev->name, ETH_NAME_LEN, "DPMAC%d@%s", priv->dpmac_id, + phy_interface_strings[enet_if]); net_dev->iobase = 0; net_dev->init = ldpaa_eth_open; -- cgit v1.2.3 From 1666fa587bfaa5ab72ea7bb9e2a811494c2a3e7b Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Thu, 2 Aug 2018 16:31:29 +0530 Subject: net: Increase ethernet name string size to 20 chars The 16 char ethernet name size is inadequate to hold the name of ethernet name "DPMAC17@rgmii-id", which is a valid name in LX2160AQDS/LX2160ARDB. Therefore, increase the name string size to 20 chars. Reported-by: Ioana Ciornei Suggested-by: Ioana Ciocoi Radulescu Signed-off-by: Pankaj Bansal Reviewed-by: York Sun --- include/net.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/net.h b/include/net.h index 62f82c4dca7..2b2deb5aaef 100644 --- a/include/net.h +++ b/include/net.h @@ -164,7 +164,7 @@ void eth_halt_state_only(void); /* Set passive state */ #ifndef CONFIG_DM_ETH struct eth_device { -#define ETH_NAME_LEN 16 +#define ETH_NAME_LEN 20 char name[ETH_NAME_LEN]; unsigned char enetaddr[ARP_HLEN]; phys_addr_t iobase; -- cgit v1.2.3 From fa0706ef92dc680f16b96659f1177822a3335bb4 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:42 +0300 Subject: armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 5b4767e0fe2..644a16dd30b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -88,8 +88,12 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) + #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) + #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL -- cgit v1.2.3 From 5bdfdb7d4fc23fdc458c0f51fe39f0b9c47a2744 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:43 +0300 Subject: armv8: ls1046a: advertise QMan v3 in configuration The QMan IP block in this SoC is version 3.2 so advertise this in the SoC configuration header. Reviewed-by: Bharat Bhushan Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 23faffd9fc6..8a051481365 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -257,6 +257,7 @@ #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 -- cgit v1.2.3 From 92d2e89c8c44a8f41d5f296e46c9cd6c9b34e4f8 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:44 +0300 Subject: misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +-- drivers/misc/fsl_portals.c | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 644a16dd30b..d22ec70aa55 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -57,8 +57,7 @@ #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 -#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \ - CONFIG_SYS_QMAN_MEM_BASE) +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 7c22b8d2099..22faf16751e 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -24,7 +24,6 @@ void setup_qbman_portals(void) CONFIG_SYS_BMAN_SWP_ISDR_REG; void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + CONFIG_SYS_QMAN_SWP_ISDR_REG; -#ifdef CONFIG_PPC struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ @@ -32,7 +31,6 @@ void setup_qbman_portals(void) out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); #endif out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); -#endif #ifdef CONFIG_FSL_CORENET int i; -- cgit v1.2.3 From 703d18f7fe0186ef7e30820030d5e5edd7123f97 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:45 +0300 Subject: armv8: fsl-layerscape: add missing debug stream ID Add a define with a value for the missing debug stream ID. Reviewed-by: Bharat Bhushan Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index 61c6e533c6c..1b02d484d98 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -50,6 +50,7 @@ #define FSL_QDMA_STREAM_ID 7 #define FSL_EDMA_STREAM_ID 8 #define FSL_ETR_STREAM_ID 9 +#define FSL_DEBUG_STREAM_ID 10 /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 11 -- cgit v1.2.3 From 3cb4fe65f9e88c6cfea2fea5ca934acfa3c415b4 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:46 +0300 Subject: armv8: ls1046a: initial icid setup support Add infrastructure for ICID setup and device tree fixup on ARM platforms. This include basic ICID setup for several devices. Reviewed-by: Bharat Bhushan Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/icid.c | 110 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 29 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 + .../arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 80 +++++++++++++++ board/freescale/ls1046aqds/ls1046aqds.c | 3 + board/freescale/ls1046ardb/ls1046ardb.c | 3 + 7 files changed, 231 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 1e9e4680fe1..5d6f68aad67 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -37,6 +37,7 @@ endif ifneq ($(CONFIG_ARCH_LS1046A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o +obj-y += icid.o ls1046_ids.o endif ifneq ($(CONFIG_ARCH_LS1088A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c new file mode 100644 index 00000000000..ae3b8daa956 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include + +#include +#include +#include + +static void set_icid(struct icid_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); +} + +void set_icids(void) +{ + /* setup general icid offsets */ + set_icid(icid_tbl, icid_tbl_sz); +} + +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids) +{ + int i, ret; + u32 prop[8]; + + /* + * Note: The "iommus" property definition mentions Stream IDs while + * this code handles ICIDs. The current implementation assumes that + * ICIDs and Stream IDs are equal. + */ + for (i = 0; i < num_ids; i++) { + prop[i * 2] = cpu_to_fdt32(smmu_ph); + prop[i * 2 + 1] = cpu_to_fdt32(ids[i]); + } + ret = fdt_setprop(blob, off, "iommus", + prop, sizeof(u32) * num_ids * 2); + if (ret) { + printf("WARNING unable to set iommus: %s\n", fdt_strerror(ret)); + return ret; + } + + return 0; +} + +int fdt_fixup_icid_tbl(void *blob, int smmu_ph, + struct icid_id_table *tbl, int size) +{ + int i, err, off; + + for (i = 0; i < size; i++) { + if (!tbl[i].compat) + continue; + + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat, + tbl[i].compat_addr); + if (off > 0) { + err = fdt_set_iommu_prop(blob, off, smmu_ph, + &tbl[i].id, 1); + if (err) + return err; + } else { + printf("WARNING could not find node %s: %s.\n", + tbl[i].compat, fdt_strerror(off)); + } + } + + return 0; +} + +int fdt_get_smmu_phandle(void *blob) +{ + int noff, smmu_ph; + + noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500"); + if (noff < 0) { + printf("WARNING failed to get smmu node: %s\n", + fdt_strerror(noff)); + return noff; + } + + smmu_ph = fdt_get_phandle(blob, noff); + if (!smmu_ph) { + smmu_ph = fdt_create_phandle(blob, noff); + if (!smmu_ph) { + printf("WARNING failed to get smmu phandle\n"); + return -1; + } + } + + return smmu_ph; +} + +void fdt_fixup_icid(void *blob) +{ + int smmu_ph; + + smmu_ph = fdt_get_smmu_phandle(blob); + if (smmu_ph < 0) + return; + + fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz); +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c new file mode 100644 index 00000000000..1c528ab751e --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include + +struct icid_id_table icid_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START), + SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), +#endif + + SET_SDHC_ICID(FSL_SDHC_STREAM_ID), + + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID), + + SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID), + SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID), + SET_EDMA_ICID(FSL_EDMA_STREAM_ID), + SET_ETR_ICID(FSL_ETR_STREAM_ID), + SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8028d5228f4..2f306c509ab 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -11,6 +11,7 @@ #include #include #include +#include #ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include #endif @@ -623,6 +624,10 @@ void fsl_lsch2_early_init_f(void) erratum_a009798(); erratum_a008997(); erratum_a009007(); + +#ifdef CONFIG_ARCH_LS1046A + set_icids(); +#endif } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h new file mode 100644 index 00000000000..57909392eab --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _FSL_ICID_H_ +#define _FSL_ICID_H_ + +#include +#include + +struct icid_id_table { + const char *compat; + u32 id; + u32 reg; + phys_addr_t compat_addr; + phys_addr_t reg_addr; +}; + +u32 get_ppid_icid(int ppid_tbl_idx, int ppid); +int fdt_get_smmu_phandle(void *blob); +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); +void set_icids(void); +void fdt_fixup_icid(void *blob); + +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \ + { .compat = name, \ + .id = idA, \ + .reg = regA, \ + .compat_addr = compataddr, \ + .reg_addr = addr, \ + } + +#define SET_SCFG_ICID(compat, streamid, name, compataddr) \ + SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ + offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ + compataddr) + +#define SET_USB_ICID(usb_num, compat, streamid) \ + SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ + CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + +#define SET_SATA_ICID(compat, streamid) \ + SET_SCFG_ICID(compat, streamid, sata_icid,\ + AHCI_BASE_ADDR) + +#define SET_SDHC_ICID(streamid) \ + SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ + CONFIG_SYS_FSL_ESDHC_ADDR) + +#define SET_QDMA_ICID(compat, streamid) \ + SET_SCFG_ICID(compat, streamid, dma_icid,\ + QDMA_BASE_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ + EDMA_BASE_ADDR) + +#define SET_ETR_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, etr_icid, 0) + +#define SET_DEBUG_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, debug_icid, 0) + +#define SET_QMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ + offsetof(struct ccsr_qman, liodnr) + \ + CONFIG_SYS_FSL_QMAN_ADDR, \ + CONFIG_SYS_FSL_QMAN_ADDR) + +#define SET_BMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ + offsetof(struct ccsr_bman, liodnr) + \ + CONFIG_SYS_FSL_BMAN_ADDR, \ + CONFIG_SYS_FSL_BMAN_ADDR) + +extern struct icid_id_table icid_tbl[]; +extern int icid_tbl_sz; + +#endif diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index b765f07f85a..0da82381af6 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -309,6 +310,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); + reg = QIXIS_READ(brdcfg[0]); reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index feb5c2448a0..0a73fe859d9 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -174,6 +175,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); #endif + fdt_fixup_icid(blob); + return 0; } #endif -- cgit v1.2.3 From 599a97d49cee04aaa6c2c8cbecc4f47a7c088dbe Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:47 +0300 Subject: armv8: ls1046a: add icid setup for qman portals Add support for ICID setting of qman portals and the required device tree fixups. Also fix an endiness issue in portal setup code. Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 ++++++++ .../include/asm/arch-fsl-layerscape/fsl_portals.h | 24 ++++++++++++ drivers/misc/fsl_portals.c | 43 ++++++++++++++++++++-- 3 files changed, 79 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index 1c528ab751e..80e1ceadc0b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -6,6 +6,22 @@ #include #include #include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), +}; +#endif struct icid_id_table icid_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h new file mode 100644 index 00000000000..1577e935a60 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _FSL_PORTALS_H_ +#define _FSL_PORTALS_H_ + +struct qportal_info { + u16 dicid; /* DQRR ICID */ + u16 ficid; /* frame data ICID */ + u16 icid; + u8 sdest; +}; + +#define SET_QP_INFO(streamid, dest) \ + { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \ + .sdest = (dest) } + +extern struct qportal_info qp_info[]; +void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size); + +#endif diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 22faf16751e..d3137680ade 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -13,6 +13,9 @@ #ifdef CONFIG_PPC #include #include +#else +#include +#include #endif #include @@ -45,6 +48,22 @@ void setup_qbman_portals(void) /* set frame liodn */ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); } +#else +#ifdef CONFIG_ARCH_LS1046A + int i; + + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + u8 sdest = qp_info[i].sdest; + u16 ficid = qp_info[i].ficid; + u16 dicid = qp_info[i].dicid; + u16 icid = qp_info[i].icid; + + out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) | + dicid); + /* set frame icid */ + out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid); + } +#endif #endif /* Change default state of BMan ISDR portals to all 1s */ @@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob) char compat[64]; int compat_len; +#ifdef CONFIG_ARCH_LS1046A + int smmu_ph = fdt_get_smmu_phandle(blob); +#endif + maj = (rev_1 >> 8) & 0xff; min = rev_1 & 0xff; ip_cfg = rev_2 & 0xff; @@ -188,7 +211,7 @@ void fdt_fixup_qportals(void *blob) off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { -#ifdef CONFIG_PPC +#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1046A) #ifdef CONFIG_FSL_CORENET u32 liodns[2]; #endif @@ -198,12 +221,12 @@ void fdt_fixup_qportals(void *blob) if (!ci) goto err; - i = *ci; -#ifdef CONFIG_SYS_DPAA_FMAN + i = fdt32_to_cpu(*ci); +#if defined(CONFIG_SYS_DPAA_FMAN) && defined(CONFIG_PPC) int j; #endif -#endif /* CONFIG_PPC */ +#endif /* CONFIG_PPC || CONFIG_ARCH_LS1046A */ err = fdt_setprop(blob, off, "compatible", compat, compat_len); if (err < 0) goto err; @@ -251,6 +274,18 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; #endif +#else +#ifdef CONFIG_ARCH_LS1046A + if (smmu_ph >= 0) { + u32 icids[3]; + + icids[0] = qp_info[i].icid; + icids[1] = qp_info[i].dicid; + icids[2] = qp_info[i].ficid; + + fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3); + } +#endif #endif /* CONFIG_PPC */ err: -- cgit v1.2.3 From b50ff5e1b67d140092c52e0b31d6c288573c7cb5 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:48 +0300 Subject: armv8: ls1046a: setup fman ports ICIDs and device tree Add support for ICID setting of fman ports and the required device tree fixups. Reviewed-by: Bharat Bhushan Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 82 ++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 ++++++++ .../arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 10 +++ 3 files changed, 122 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index ae3b8daa956..b1a950e7f9c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -10,6 +10,7 @@ #include #include #include +#include static void set_icid(struct icid_id_table *tbl, int size) { @@ -19,10 +20,27 @@ static void set_icid(struct icid_id_table *tbl, int size) out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); } +#ifdef CONFIG_SYS_DPAA_FMAN +void set_fman_icids(struct fman_icid_id_table *tbl, int size) +{ + int i; + ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; + + for (i = 0; i < size; i++) { + out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1], + tbl[i].icid); + } +} +#endif + void set_icids(void) { /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz); + +#ifdef CONFIG_SYS_DPAA_FMAN + set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); +#endif } int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids) @@ -75,6 +93,66 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph, return 0; } +#ifdef CONFIG_SYS_DPAA_FMAN +int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl, + const int size) +{ + int i; + + for (i = 0; i < size; i++) { + if (tbl[i].port_id == port_id) + return tbl[i].icid; + } + + return -1; +} + +void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph, + const char *compat) +{ + int noff, len, icid; + const u32 *prop; + + noff = fdt_node_offset_by_compatible(blob, -1, compat); + while (noff > 0) { + prop = fdt_getprop(blob, noff, "cell-index", &len); + if (!prop) { + printf("WARNING missing cell-index for fman port\n"); + continue; + } + if (len != 4) { + printf("WARNING bad cell-index size for fman port\n"); + continue; + } + + icid = get_fman_port_icid(fdt32_to_cpu(*prop), + fman_icid_tbl, fman_icid_tbl_sz); + if (icid < 0) { + printf("WARNING unknown ICID for fman port %d\n", + *prop); + continue; + } + + fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1); + + noff = fdt_node_offset_by_compatible(blob, noff, compat); + } +} + +void fdt_fixup_fman_icids(void *blob, int smmu_ph) +{ + static const char * const compats[] = { + "fsl,fman-v3-port-oh", + "fsl,fman-v3-port-rx", + "fsl,fman-v3-port-tx", + }; + int i; + + for (i = 0; i < ARRAY_SIZE(compats); i++) + fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph, compats[i]); +} +#endif + int fdt_get_smmu_phandle(void *blob) { int noff, smmu_ph; @@ -107,4 +185,8 @@ void fdt_fixup_icid(void *blob) return; fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_icids(blob, smmu_ph); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index 80e1ceadc0b..30c7d8d28af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -43,3 +43,33 @@ struct icid_id_table icid_tbl[] = { }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct fman_icid_id_table fman_icid_tbl[] = { + /* port id, icid */ + SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END), +}; + +int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl); +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 57909392eab..5be50a17ab8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -17,6 +17,11 @@ struct icid_id_table { phys_addr_t reg_addr; }; +struct fman_icid_id_table { + u32 port_id; + u32 icid; +}; + u32 get_ppid_icid(int ppid_tbl_idx, int ppid); int fdt_get_smmu_phandle(void *blob); int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); @@ -74,7 +79,12 @@ void fdt_fixup_icid(void *blob); CONFIG_SYS_FSL_BMAN_ADDR, \ CONFIG_SYS_FSL_BMAN_ADDR) +#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ + { .port_id = (_port_id), .icid = (streamid) } + extern struct icid_id_table icid_tbl[]; +extern struct fman_icid_id_table fman_icid_tbl[]; extern int icid_tbl_sz; +extern int fman_icid_tbl_sz; #endif -- cgit v1.2.3 From 5651f438f8ac566eb5fec7c1fe92a0282d459e60 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 9 Aug 2018 15:19:49 +0300 Subject: armv8: ls1046a: setup SEC ICIDs and fix up device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă Reviewed-by: Bharat Bhushan Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14 ++++++++++++ .../arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 25 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 +++++++ 3 files changed, 47 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index 30c7d8d28af..2da9adab5b9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -40,6 +40,20 @@ struct icid_id_table icid_tbl[] = { SET_EDMA_ICID(FSL_EDMA_STREAM_ID), SET_ETR_ICID(FSL_ETR_STREAM_ID), SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2), + SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3), + SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4), + SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5), + SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10), + SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11), + SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12), + SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 13), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 5be50a17ab8..a70c866651a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -8,6 +8,7 @@ #include #include +#include struct icid_id_table { const char *compat; @@ -82,6 +83,30 @@ void fdt_fixup_icid(void *blob); #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ { .port_id = (_port_id), .icid = (streamid) } +#define SET_SEC_QI_ICID(streamid) \ + SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ + (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, qilcr_ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, \ + CONFIG_SYS_FSL_SEC_ADDR) + +#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ + SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \ + (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, \ + FSL_SEC_JR##jr_num##_BASE_ADDR) + +#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, 0) + +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, 0) + extern struct icid_id_table icid_tbl[]; extern struct fman_icid_id_table fman_icid_tbl[]; extern int icid_tbl_sz; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d22ec70aa55..be0a6ae363f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -200,10 +200,18 @@ struct sys_info { #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x720000ull +#define FSL_SEC_JR2_OFFSET 0x730000ull +#define FSL_SEC_JR3_OFFSET 0x740000ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) /* Device Configuration and Pin Control */ #define DCFG_DCSR_PORCR1 0x0 -- cgit v1.2.3 From 1711add3dca291376072ec0c66b01023a3462daf Mon Sep 17 00:00:00 2001 From: Darwin Dingel Date: Thu, 2 Aug 2018 10:02:45 +0200 Subject: mtd: nand: fsl_ifc: Fix handling of bitflips in erased pages This is a fix made for the fsl_ifc_nand driver on linux kernel by Pavel Machek and is applied to uboot. It is currently on applied on linux-mtd. https://patchwork.kernel.org/patch/9758117/ IFC always raises ECC errors on erased pages. It is only ignored when the buffer is checked for all 0xFF by is_blank(). The problem is a single bitflip will cause is_blank() and then mtd_read to fail. The fix makes use of nand_check_erased_ecc_chunk() to check for empty pages instead of is_blank(). This also makes sure that reads are made at ECC page size granularity to get a proper bitflip count. If the number of bitflips does not exceed the ECC strength, the page is considered empty and the bitflips will be corrected when data is sent to the higher layers (e.g. ubi). Signed-off-by: Darwin Dingel Cc: Pavel Machek Cc: Scott Wood Acked-by: Pavel Machek [Kurt: Replaced dev_err by printf due to compiler warnings] Tested-by: Kurt Kanzenbach Signed-off-by: Kurt Kanzenbach Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 69 +++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 30 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index a47226bd215..29f30d8ccc4 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -242,31 +242,6 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ctrl->index += mtd->writesize; } -static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, - unsigned int bufnum) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); - u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2); - u32 __iomem *main = (u32 *)addr; - u8 __iomem *oob = addr + mtd->writesize; - int i; - - for (i = 0; i < mtd->writesize / 4; i++) { - if (__raw_readl(&main[i]) != 0xffffffff) - return 0; - } - - for (i = 0; i < chip->ecc.layout->eccbytes; i++) { - int pos = chip->ecc.layout->eccpos[i]; - - if (__raw_readb(&oob[pos]) != 0xff) - return 0; - } - - return 1; -} - /* returns nonzero if entire page is blank */ static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, u32 eccstat, unsigned int bufnum) @@ -331,16 +306,14 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) if (errors == 15) { /* * Uncorrectable error. - * OK only if the whole page is blank. + * We'll check for blank pages later. * * We disable ECCER reporting due to erratum * IFC-A002770 -- so report it now if we * see an uncorrectable error in ECCSTAT. */ - if (!is_blank(mtd, ctrl, bufnum)) - ctrl->status |= - IFC_NAND_EVTER_STAT_ECCER; - break; + ctrl->status |= IFC_NAND_EVTER_STAT_ECCER; + continue; } mtd->ecc_stats.corrected += errors; @@ -727,6 +700,39 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) return status | NAND_STATUS_WP; } +/* + * The controller does not check for bitflips in erased pages, + * therefore software must check instead. + */ +static int +check_erased_page(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd) +{ + u8 *ecc = chip->oob_poi; + const int ecc_size = chip->ecc.bytes; + const int pkt_size = chip->ecc.size; + int i, res, bitflips; + + /* IFC starts ecc bytes at offset 8 in the spare area. */ + ecc += 8; + bitflips = 0; + for (i = 0; i < chip->ecc.steps; i++) { + res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, + NULL, 0, chip->ecc.strength); + + if (res < 0) { + printf("fsl-ifc: NAND Flash ECC Uncorrectable Error\n"); + mtd->ecc_stats.failed++; + } else if (res > 0) { + mtd->ecc_stats.corrected += res; + } + bitflips = max(res, bitflips); + buf += pkt_size; + ecc += ecc_size; + } + + return bitflips; +} + static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { @@ -736,6 +742,9 @@ static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, fsl_ifc_read_buf(mtd, buf, mtd->writesize); fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); + if (ctrl->status & IFC_NAND_EVTER_STAT_ECCER) + return check_erased_page(chip, buf, mtd); + if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) mtd->ecc_stats.failed++; -- cgit v1.2.3 From cd35855492aafc4076a634a6d748bffc9e26795e Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 10 Aug 2018 14:59:59 +0800 Subject: armv8: layerscape: move ns_dev[] define from h to c file. Move ns_dev[] from header file to C file to avoid compiling warning when header file is included by others. Signed-off-by: Ran Wang [YS: rewrite commit message] Reviewed-by: York Sun --- .../include/asm/arch-fsl-layerscape/ns_access.h | 80 ---------- arch/arm/include/asm/arch-ls102xa/ns_access.h | 84 ----------- board/freescale/common/ns_access.c | 167 +++++++++++++++++++++ 3 files changed, 167 insertions(+), 164 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index 8ecff4d13ff..2bbfab7388c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -87,84 +87,4 @@ enum csu_cslx_ind { CSU_CSLX_DSCR = 121, }; -static struct csu_ns_dev ns_dev[] = { - {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, - {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, - {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, - {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, - {CSU_CSLX_OCRAM, CSU_ALL_RW}, - {CSU_CSLX_GIC, CSU_ALL_RW}, - {CSU_CSLX_PCIE1, CSU_ALL_RW}, - {CSU_CSLX_OCRAM2, CSU_ALL_RW}, - {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, - {CSU_CSLX_PCIE2, CSU_ALL_RW}, - {CSU_CSLX_SATA, CSU_ALL_RW}, - {CSU_CSLX_USB1, CSU_ALL_RW}, - {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, - {CSU_CSLX_PCIE3, CSU_ALL_RW}, - {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, - {CSU_CSLX_USB3, CSU_ALL_RW}, - {CSU_CSLX_USB2, CSU_ALL_RW}, - {CSU_CSLX_PFE, CSU_ALL_RW}, - {CSU_CSLX_SERDES, CSU_ALL_RW}, - {CSU_CSLX_QDMA, CSU_ALL_RW}, - {CSU_CSLX_LPUART2, CSU_ALL_RW}, - {CSU_CSLX_LPUART1, CSU_ALL_RW}, - {CSU_CSLX_LPUART4, CSU_ALL_RW}, - {CSU_CSLX_LPUART3, CSU_ALL_RW}, - {CSU_CSLX_LPUART6, CSU_ALL_RW}, - {CSU_CSLX_LPUART5, CSU_ALL_RW}, - {CSU_CSLX_DSPI1, CSU_ALL_RW}, - {CSU_CSLX_QSPI, CSU_ALL_RW}, - {CSU_CSLX_ESDHC, CSU_ALL_RW}, - {CSU_CSLX_IFC, CSU_ALL_RW}, - {CSU_CSLX_I2C1, CSU_ALL_RW}, - {CSU_CSLX_I2C3, CSU_ALL_RW}, - {CSU_CSLX_I2C2, CSU_ALL_RW}, - {CSU_CSLX_DUART2, CSU_ALL_RW}, - {CSU_CSLX_DUART1, CSU_ALL_RW}, - {CSU_CSLX_WDT2, CSU_ALL_RW}, - {CSU_CSLX_WDT1, CSU_ALL_RW}, - {CSU_CSLX_EDMA, CSU_ALL_RW}, - {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, - {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, - {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, - {CSU_CSLX_DDR, CSU_ALL_RW}, - {CSU_CSLX_QUICC, CSU_ALL_RW}, - {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, - {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, - {CSU_CSLX_SFP, CSU_ALL_RW}, - {CSU_CSLX_TMU, CSU_ALL_RW}, - {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, - {CSU_CSLX_SCFG, CSU_ALL_RW}, - {CSU_CSLX_FM, CSU_ALL_RW}, - {CSU_CSLX_SEC5_5, CSU_ALL_RW}, - {CSU_CSLX_BM, CSU_ALL_RW}, - {CSU_CSLX_QM, CSU_ALL_RW}, - {CSU_CSLX_GPIO2, CSU_ALL_RW}, - {CSU_CSLX_GPIO1, CSU_ALL_RW}, - {CSU_CSLX_GPIO4, CSU_ALL_RW}, - {CSU_CSLX_GPIO3, CSU_ALL_RW}, - {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, - {CSU_CSLX_CSU, CSU_ALL_RW}, - {CSU_CSLX_IIC4, CSU_ALL_RW}, - {CSU_CSLX_WDT4, CSU_ALL_RW}, - {CSU_CSLX_WDT3, CSU_ALL_RW}, - {CSU_CSLX_ESDHC2, CSU_ALL_RW}, - {CSU_CSLX_WDT5, CSU_ALL_RW}, - {CSU_CSLX_SAI2, CSU_ALL_RW}, - {CSU_CSLX_SAI1, CSU_ALL_RW}, - {CSU_CSLX_SAI4, CSU_ALL_RW}, - {CSU_CSLX_SAI3, CSU_ALL_RW}, - {CSU_CSLX_FTM2, CSU_ALL_RW}, - {CSU_CSLX_FTM1, CSU_ALL_RW}, - {CSU_CSLX_FTM4, CSU_ALL_RW}, - {CSU_CSLX_FTM3, CSU_ALL_RW}, - {CSU_CSLX_FTM6, CSU_ALL_RW}, - {CSU_CSLX_FTM5, CSU_ALL_RW}, - {CSU_CSLX_FTM8, CSU_ALL_RW}, - {CSU_CSLX_FTM7, CSU_ALL_RW}, - {CSU_CSLX_DSCR, CSU_ALL_RW}, -}; - #endif diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h index f414b736d04..b6daf32e56a 100644 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -91,88 +91,4 @@ enum csu_cslx_ind { CSU_CSLX_MAX, }; -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; - #endif diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index 79fa6aa2e75..0e6f2135b4a 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -9,6 +9,173 @@ #include #include +#ifdef CONFIG_ARCH_LS1021A +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; + +#else +static struct csu_ns_dev ns_dev[] = { + {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, + {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, + {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, + {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, + {CSU_CSLX_OCRAM, CSU_ALL_RW}, + {CSU_CSLX_GIC, CSU_ALL_RW}, + {CSU_CSLX_PCIE1, CSU_ALL_RW}, + {CSU_CSLX_OCRAM2, CSU_ALL_RW}, + {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, + {CSU_CSLX_PCIE2, CSU_ALL_RW}, + {CSU_CSLX_SATA, CSU_ALL_RW}, + {CSU_CSLX_USB1, CSU_ALL_RW}, + {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, + {CSU_CSLX_PCIE3, CSU_ALL_RW}, + {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, + {CSU_CSLX_USB3, CSU_ALL_RW}, + {CSU_CSLX_USB2, CSU_ALL_RW}, + {CSU_CSLX_PFE, CSU_ALL_RW}, + {CSU_CSLX_SERDES, CSU_ALL_RW}, + {CSU_CSLX_QDMA, CSU_ALL_RW}, + {CSU_CSLX_LPUART2, CSU_ALL_RW}, + {CSU_CSLX_LPUART1, CSU_ALL_RW}, + {CSU_CSLX_LPUART4, CSU_ALL_RW}, + {CSU_CSLX_LPUART3, CSU_ALL_RW}, + {CSU_CSLX_LPUART6, CSU_ALL_RW}, + {CSU_CSLX_LPUART5, CSU_ALL_RW}, + {CSU_CSLX_DSPI1, CSU_ALL_RW}, + {CSU_CSLX_QSPI, CSU_ALL_RW}, + {CSU_CSLX_ESDHC, CSU_ALL_RW}, + {CSU_CSLX_IFC, CSU_ALL_RW}, + {CSU_CSLX_I2C1, CSU_ALL_RW}, + {CSU_CSLX_I2C3, CSU_ALL_RW}, + {CSU_CSLX_I2C2, CSU_ALL_RW}, + {CSU_CSLX_DUART2, CSU_ALL_RW}, + {CSU_CSLX_DUART1, CSU_ALL_RW}, + {CSU_CSLX_WDT2, CSU_ALL_RW}, + {CSU_CSLX_WDT1, CSU_ALL_RW}, + {CSU_CSLX_EDMA, CSU_ALL_RW}, + {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, + {CSU_CSLX_DDR, CSU_ALL_RW}, + {CSU_CSLX_QUICC, CSU_ALL_RW}, + {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, + {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, + {CSU_CSLX_SFP, CSU_ALL_RW}, + {CSU_CSLX_TMU, CSU_ALL_RW}, + {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, + {CSU_CSLX_SCFG, CSU_ALL_RW}, + {CSU_CSLX_FM, CSU_ALL_RW}, + {CSU_CSLX_SEC5_5, CSU_ALL_RW}, + {CSU_CSLX_BM, CSU_ALL_RW}, + {CSU_CSLX_QM, CSU_ALL_RW}, + {CSU_CSLX_GPIO2, CSU_ALL_RW}, + {CSU_CSLX_GPIO1, CSU_ALL_RW}, + {CSU_CSLX_GPIO4, CSU_ALL_RW}, + {CSU_CSLX_GPIO3, CSU_ALL_RW}, + {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, + {CSU_CSLX_CSU, CSU_ALL_RW}, + {CSU_CSLX_IIC4, CSU_ALL_RW}, + {CSU_CSLX_WDT4, CSU_ALL_RW}, + {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_ESDHC2, CSU_ALL_RW}, + {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_SAI2, CSU_ALL_RW}, + {CSU_CSLX_SAI1, CSU_ALL_RW}, + {CSU_CSLX_SAI4, CSU_ALL_RW}, + {CSU_CSLX_SAI3, CSU_ALL_RW}, + {CSU_CSLX_FTM2, CSU_ALL_RW}, + {CSU_CSLX_FTM1, CSU_ALL_RW}, + {CSU_CSLX_FTM4, CSU_ALL_RW}, + {CSU_CSLX_FTM3, CSU_ALL_RW}, + {CSU_CSLX_FTM6, CSU_ALL_RW}, + {CSU_CSLX_FTM5, CSU_ALL_RW}, + {CSU_CSLX_FTM8, CSU_ALL_RW}, + {CSU_CSLX_FTM7, CSU_ALL_RW}, + {CSU_CSLX_DSCR, CSU_ALL_RW}, +}; +#endif + void set_devices_ns_access(unsigned long index, u16 val) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; -- cgit v1.2.3 From 9add5a4b75a01cc5f69b9d5f6b30443f2088d7d8 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 10 Aug 2018 15:00:00 +0800 Subject: armv8: layerscape: Enable EHCI access for LS1012A Program Central Security Unit (CSU) to grant access to USB 2.0 controller. Signed-off-by: Ran Wang [YS: rewrite commit message] Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++ arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2f306c509ab..3f15cb08ffb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include @@ -615,6 +616,14 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); } + /* + * Program Central Security Unit (CSU) to grant access + * permission for USB 2.0 controller + */ +#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL) + if (current_el() == 3) + set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW); +#endif /* Erratum */ erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index 2bbfab7388c..a265106686d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -39,6 +39,7 @@ enum csu_cslx_ind { CSU_CSLX_ESDHC, CSU_CSLX_IFC = 45, CSU_CSLX_I2C1, + CSU_CSLX_USB_2, CSU_CSLX_I2C3 = 48, CSU_CSLX_I2C2, CSU_CSLX_DUART2 = 50, -- cgit v1.2.3