From a75dd7f7df968300e0213ff7f8cbc987df344d4c Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 22 Apr 2015 19:23:07 +0200 Subject: Colibri iMX6: initial commit use make colibri_imx6_defconfig --- arch/arm/Kconfig | 5 + board/toradex/colibri_imx6/800mhz_2x64mx16.cfg | 58 ++ board/toradex/colibri_imx6/800mhz_4x64mx16.cfg | 58 ++ board/toradex/colibri_imx6/Kconfig | 33 ++ board/toradex/colibri_imx6/MAINTAINERS | 8 + board/toradex/colibri_imx6/Makefile | 6 + board/toradex/colibri_imx6/clocks.cfg | 41 ++ board/toradex/colibri_imx6/colibri_imx6.c | 644 +++++++++++++++++++++ board/toradex/colibri_imx6/colibri_imx6.cfg | 38 ++ board/toradex/colibri_imx6/ddr-setup.cfg | 97 ++++ board/toradex/colibri_imx6/do_fuse.c | 54 ++ board/toradex/colibri_imx6/pf0100.c | 224 +++++++ board/toradex/colibri_imx6/pf0100.h | 55 ++ board/toradex/colibri_imx6/pf0100_otp.inc | 189 ++++++ .../colibri_imx6/pf0100_otp_Colibri_iMX6.txt | 189 ++++++ configs/colibri_imx6_defconfig | 3 + include/configs/colibri_imx6.h | 325 +++++++++++ 17 files changed, 2027 insertions(+) create mode 100644 board/toradex/colibri_imx6/800mhz_2x64mx16.cfg create mode 100644 board/toradex/colibri_imx6/800mhz_4x64mx16.cfg create mode 100644 board/toradex/colibri_imx6/Kconfig create mode 100644 board/toradex/colibri_imx6/MAINTAINERS create mode 100644 board/toradex/colibri_imx6/Makefile create mode 100644 board/toradex/colibri_imx6/clocks.cfg create mode 100644 board/toradex/colibri_imx6/colibri_imx6.c create mode 100644 board/toradex/colibri_imx6/colibri_imx6.cfg create mode 100644 board/toradex/colibri_imx6/ddr-setup.cfg create mode 100644 board/toradex/colibri_imx6/do_fuse.c create mode 100644 board/toradex/colibri_imx6/pf0100.c create mode 100644 board/toradex/colibri_imx6/pf0100.h create mode 100644 board/toradex/colibri_imx6/pf0100_otp.inc create mode 100644 board/toradex/colibri_imx6/pf0100_otp_Colibri_iMX6.txt create mode 100644 configs/colibri_imx6_defconfig create mode 100644 include/configs/colibri_imx6.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7278979c1fa..1747c226d66 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -502,6 +502,10 @@ config TARGET_APALIS_IMX6 bool "Toradex Apalis iMX6 board" select CPU_V7 +config TARGET_COLIBRI_IMX6 + bool "Toradex Colibri iMX6 board" + select CPU_V7 + config TARGET_CGTQMX6EVAL bool "Support cgtqmx6eval" select CPU_V7 @@ -883,6 +887,7 @@ source "board/ti/ti814x/Kconfig" source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/apalis_imx6/Kconfig" +source "board/toradex/colibri_imx6/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" source "board/toradex/common/Kconfig" diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg new file mode 100644 index 00000000000..1ec514dd4ec --- /dev/null +++ b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +/* DDR3 DATA BUS SIZE: 64BIT */ +/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */ +/* DDR3 DATA BUS SIZE: 32BIT */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 + +/* Write commands to DDR */ +/* Load Mode Registers */ +/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ +/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 + +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 + +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg new file mode 100644 index 00000000000..3173e1c9ab4 --- /dev/null +++ b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +/* DDR3 DATA BUS SIZE: 64BIT */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 +/* DDR3 DATA BUS SIZE: 32BIT */ +/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */ + +/* Write commands to DDR */ +/* Load Mode Registers */ +/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ +/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 + +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 + +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig new file mode 100644 index 00000000000..ff6af7a2b07 --- /dev/null +++ b/board/toradex/colibri_imx6/Kconfig @@ -0,0 +1,33 @@ +if TARGET_COLIBRI_IMX6 + +config SYS_BOARD + default "colibri_imx6" + +config SYS_CONFIG_NAME + default "colibri_imx6" + +config SYS_CPU + default "armv7" + +config SYS_SOC + default "mx6" + +config SYS_VENDOR + default "toradex" + +config TRDX_CFG_BLOCK + default y + +config TRDX_HAVE_MMC + default y + +config TRDX_CFG_BLOCK_DEV + default "0" + +config TRDX_CFG_BLOCK_PART + default "0" + +config TRDX_CFG_BLOCK_OFFSET + default "655360" + +endif diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS new file mode 100644 index 00000000000..4dd116f715b --- /dev/null +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -0,0 +1,8 @@ +Colibri iMX6 +M: Max Krummenacher +M: Toradex ARM Support +W: http://developer.toradex.com/software-resources/arm-family/linux +S: Maintained +F: board/toradex/colibri_imx6/ +F: include/configs/colibri_imx6.h +F: configs/colibri_imx6_defconfig diff --git a/board/toradex/colibri_imx6/Makefile b/board/toradex/colibri_imx6/Makefile new file mode 100644 index 00000000000..7c22750228e --- /dev/null +++ b/board/toradex/colibri_imx6/Makefile @@ -0,0 +1,6 @@ +# Copyright (c) 2012-2014 Toradex, Inc. +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := colibri_imx6.o +obj-y += pf0100.o +obj-y += do_fuse.o diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg new file mode 100644 index 00000000000..8bddb91d77c --- /dev/null +++ b/board/toradex/colibri_imx6/clocks.cfg @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c new file mode 100644 index 00000000000..a0809eefa5f --- /dev/null +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -0,0 +1,644 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices + * Copyright (C) 2014-2015, Toradex AG + * copied from nitrogen6x + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/configblock.h" +#include "pf0100.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +u32 get_board_rev(void); + +int dram_init(void) +{ + /* use the DDR controllers configured size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + (ulong)imx_ddr_size()); + + return 0; +} + +/* Colibri UARTA */ +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* Colibri I2C */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* Colibri local, PMIC, SGTL5000, STMPE811*/ +struct i2c_pads_info i2c_pad_info_loc = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* Apalis MMC */ +iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +# define GPIO_MMC_CD IMX_GPIO_NR(2, 5) +}; + +/* eMMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +iomux_v3_cfg_t const usb_pads[] = { + /* TODO This pin has a dedicated USB power functionality, can we use it? */ + /* USB_PE */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define GPIO_USBH_EN IMX_GPIO_NR(3, 31) +#if 0 +/* FIXME USB CLIENT */ + /* USB_C_DET */ + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), +#endif +}; + +/* UARTs are used in DTE mode, switch the mode on all UARTs before + * any pinmuxing connects a (DCE) output to a transceiver output. + */ +#define UFCR 0x90 /* FIFO Control Register */ +#define UFCR_DCEDTE (1<<6) /* DCE=0 */ + +static void setup_dtemode_uart(void) +{ + setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); + setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); + setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE); +} + +static void setup_iomux_uart(void) +{ + setup_dtemode_uart(); + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + /* control OTG power */ + /* No special PE for USBC, always on when ID pin signals host mode */ + break; + case 1: + /* Control MXM USBH */ + /* Set MXM USBH power enable, '0' means on */ + gpio_direction_output(GPIO_USBH_EN, !on); + mdelay(100); + break; + default: + break; + } + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +/* use the following sequence: eMMC, MMC */ +struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = true; /* default: assume inserted */ + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + gpio_direction_input(GPIO_MMC_CD); + ret = !gpio_get_value(GPIO_MMC_CD); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].max_bus_width = 4; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + //provide the phy clock from the i.mx6 + ret = enable_fec_anatop_clock(ENET_50MHZ); + if (ret) + return ret; + /* set gpr1[ENET_CLK_SEL] */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 1..7 */ + phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); + if (!phydev) { + free(bus); + puts("no phy found\n"); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +static iomux_v3_cfg_t const pwr_intb_pads[] = { + /* the bootrom sets the iomux to vselect, potentially connecting + * two outputs. Set this back to GPIO */ + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +#if defined(CONFIG_VIDEO_IPUV3) + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight On */ + MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26) +/* TODO PWM not GPIO */ + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9) +}; + +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, +}; + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); + gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "vga-rgb", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39682, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); +/* FIXME disable whatever LVDS stuff is initialized here */ + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* backlights unconditionally on for now */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + /* use 0 for EDT 7", use 1 for LG fullHD panel */ + gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); +} +#endif /* defined(CONFIG_VIDEO_IPUV3) */ + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(pwr_intb_pads, + ARRAY_SIZE(pwr_intb_pads)); + setup_iomux_uart(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); + + (void) pmic_init(); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + char env_str[256]; + u32 rev; + +#if defined(CONFIG_REVISION_TAG) && defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) + rev = get_board_rev(); + snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); + setenv("board_rev", env_str); +#endif + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ + +int checkboard(void) +{ +#ifdef CONFIG_TRDX_CFG_BLOCK + if (read_trdx_cfg_block()) + printf("Missing Toradex config block\n"); + else { + display_board_info(); + return 0; + } +#endif + printf("Model: Toradex Colibri iMX6 %sMB\n", (gd->ram_size == 0x20000000)?"512":"256"); + return 0; +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + unsigned short prodnr = 0; + unsigned short usb_pid; + /* assume a maximum 64bit serial */ + char serialnr[21]; + + get_board_product_number(&prodnr); + + put_unaligned(CONFIG_TRDX_VID, &dev->idVendor); + + usb_pid = prodnr + 0x100; + put_unaligned(usb_pid, &dev->idProduct); + + get_board_serial_char(serialnr); + g_dnl_set_serialnumber(serialnr); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} + +/* On Colibri iMX6 the DDR bus width depends on the CPU type + * With Solo it is 32bit, with Dual Light 64 bit. + * U-Boot is configured to use 32bit on both models which works. + * This commands patches this so that on subsequent boots a DL + * will use 64bit and thus all stuffed memory + */ +int do_patch_ddr_size(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + char *ivt; + struct mmc *mmc; + int ret = 0; + + ivt = memalign(ARCH_DMA_MINALIGN, 1024); + if (ivt != NULL) { + /* read IVT */ + mmc = find_mmc_device(0); + ret = mmc->block_dev.block_read(0, 2, 2, ivt); + /* FIXME: Parse IVT to find DCD, parse DCD to find correct write addr */ + if(ret == 2) { + if(is_cpu_type(MXC_CPU_MX6DL) && (ivt[0x215] == 0x19)) { + ivt[0x215] = 0x1a; + ret = mmc->block_dev.block_write(0, 2, 2, ivt); + puts("patched, "); + } + } + } + if(ret == 2) + puts("done.\n"); + else + puts("failed.\n"); + return 0; +} + +U_BOOT_CMD( + patch_ddr_size, 1, 0, do_patch_ddr_size, + "Patch the DCD table to the right ddr size depending on CPU type\n", + "" +); diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg new file mode 100644 index 00000000000..e7886de3f0b --- /dev/null +++ b/board/toradex/colibri_imx6/colibri_imx6.cfg @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" + +#if CONFIG_DDR_MB == 256 +#include "800mhz_2x64mx16.cfg" +#elif CONFIG_DDR_MB == 512 +#include "800mhz_4x64mx16.cfg" +#else +#error "unknown DDR size" +#endif + +#include "clocks.cfg" diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg new file mode 100644 index 00000000000..78e68f37c50 --- /dev/null +++ b/board/toradex/colibri_imx6/ddr-setup.cfg @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +/* TODO: check what the RALAT field does */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c new file mode 100644 index 00000000000..2b918e5d5a4 --- /dev/null +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2014, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for i.MX OTP fusing during module production +*/ + +#include +#include + +static unsigned mfgr_fuse(void); +unsigned mfgr_fuse(void) +{ + unsigned val, val6; + + fuse_sense(0, 5, &val); + printf("Fuse 0, 5: %8x\n", val); + fuse_sense(0, 6, &val6); + printf("Fuse 0, 6: %8x\n", val6); + fuse_sense(4, 3, &val); + printf("Fuse 4, 3: %8x\n", val); + fuse_sense(4, 2, &val); + printf("Fuse 4, 2: %8x\n", val); + if(val6 & 0x10) + { + puts("BT_FUSE_SEL already fused, will do nothing\n"); + return 1; + } + /* boot cfg */ + fuse_prog(0, 5, 0x00005062); + /* BT_FUSE_SEL */ + fuse_prog(0, 6, 0x00000010); + return 0; +} + +int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + puts("Fusing...\n"); + if(!mfgr_fuse()) + puts("done.\n"); + else + puts("failed.\n"); + return 0; +} + +U_BOOT_CMD( + mfgr_fuse, 1, 0, do_mfgr_fuse, + "OTP fusing during module production\n", + "" +); diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c new file mode 100644 index 00000000000..e26b5b1d96e --- /dev/null +++ b/board/toradex/colibri_imx6/pf0100.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2014, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for Freescale PMIC PF0100 +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "pf0100_otp.inc" +#include "pf0100.h" + +/* define for PMIC register dump */ +/*#define DEBUG */ + +/* 7-bit I2C bus slave address */ +#define PFUZE100_I2C_ADDR (0x08) + +/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */ +static iomux_v3_cfg_t const pmic_prog_pads[] = { + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3) +}; + +unsigned pmic_init(void) +{ + unsigned programmed = 0; + uchar bus = 1; + uchar devid, revid, val; + + puts("PMIC: "); + if(!(0 == i2c_set_bus_num(bus) && (0 == i2c_probe(PFUZE100_I2C_ADDR)))) + { + puts("i2c bus failed\n"); + return 0; + } + /* get device ident */ + if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) + { + puts("i2c pmic devid read failed\n"); + return 0; + } + if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) + { + puts("i2c pmic revid read failed\n"); + return 0; + } + printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); + +#ifdef DEBUG + { + unsigned i,j; + + for(i=0; i<16; i++) + printf("\t%x",i); + for(j=0; j<0x80; ) + { + printf("\n%2x",j); + for(i=0; i<16; i++) + { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 1"); + + val = PFUZE100_PAGE_REGISTER_PAGE1; + if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) + { + puts("i2c write failed\n"); + return 0; + } + + for(j=0x80; j<0x100; ) + { + printf("\n%2x",j); + for(i=0; i<16; i++) + { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 2"); + + val = PFUZE100_PAGE_REGISTER_PAGE2; + if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) + { + puts("i2c write failed\n"); + return 0; + } + + for(j=0x80; j<0x100; ) + { + printf("\n%2x",j); + for(i=0; i<16; i++) + { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\n"); + } +#endif + /* get device programmed state */ + val = PFUZE100_PAGE_REGISTER_PAGE1; + if( i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) + { + puts("i2c write failed\n"); + return 0; + } + if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) + { + puts("i2c fuse_por read failed\n"); + return 0; + } + if(val & PFUZE100_FUSE_POR_M) + programmed++; + + if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) + { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if(val & PFUZE100_FUSE_POR_M) + programmed++; + + if( i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) + { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if(val & PFUZE100_FUSE_POR_M) + programmed++; + + switch (programmed) { + case 0: + printf("PMIC: not programmed\n"); + break; + case 3: + printf("PMIC: programmed\n"); + break; + default: + printf("PMIC: undefined programming state\n"); + break; + } + + return programmed; +} + +int pf0100_prog(void) +{ + unsigned char bus = 1; + unsigned char val; + unsigned i; + + if(pmic_init() == 3) { + puts("PMIC already programmed, exiting\n"); + return 1; + } + /* set up gpio to manipulate vprog, initially off */ + imx_iomux_v3_setup_multiple_pads(pmic_prog_pads, ARRAY_SIZE(pmic_prog_pads)); + gpio_direction_output(PMIC_PROG_VOLTAGE, 0); + + if(!(0 == i2c_set_bus_num(bus) && (0 == i2c_probe(PFUZE100_I2C_ADDR)))) + { + puts("i2c bus failed\n"); + return 1; + } + + for (i=0; i pf0100_otp.inc + sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc + sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ + +enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; +struct pmic_otp_prog_t{ + unsigned char cmd; + unsigned char reg; + unsigned short value; +}; + +struct pmic_otp_prog_t pmic_otp_prog[] = { +{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1 +{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94 +{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95 +{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96 +{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102 +{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103 +{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104 +{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106 +{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108 +{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110 +{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111 +{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112 +{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114 +{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115 +{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116 +{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118 +{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120 +{pmic_i2c, 0xBD, 0x08}, // Auto gen from Row123 +{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126 +{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130 +{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134 +{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138 +{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139 +{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142 +{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147 +{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150 +{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151 +{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154 +{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155 +{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158 + +#if 0 /* TBB mode */ +{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1 +{pmic_delay, 0, 10}, +#else +// Write OTP +{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1 +{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1 +{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1 +{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register +{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register +{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2 +{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register +{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST +//VPGM:DOWN:n +//VPGM:UP:n +{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up +//----------------------------------------------------------------------------------- +// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10) +//----------------------------------------------------------------------------------- +// BANK 1 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 2 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 3 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 4 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 5 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 6 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 7 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 8 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 9 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 10 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +{pmic_vpgm, 0, 0}, // Turn off 8V SWBST +{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off +{pmic_i2c, 0xD0, 0x00}, // Clear +{pmic_i2c, 0xD1, 0x00}, // Clear +{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data +{pmic_delay, 0, 500}, +{pmic_pwr, 0, 1}, +#endif +}; \ No newline at end of file diff --git a/board/toradex/colibri_imx6/pf0100_otp_Colibri_iMX6.txt b/board/toradex/colibri_imx6/pf0100_otp_Colibri_iMX6.txt new file mode 100644 index 00000000000..54f4ab065ae --- /dev/null +++ b/board/toradex/colibri_imx6/pf0100_otp_Colibri_iMX6.txt @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2014, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +// Register Output for PF0100 programmer +// Customer: Toradex AG +// Program: Colibri iMX6 +// Sample marking: +// Date: 06.08.2014 +// Time: 14:01:01 +// Generated from Spreadsheet Revision: P1.8 + +/* sed commands to get from programmer script to struct */ +/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc + sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc + sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ + +enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; +struct pmic_otp_prog_t{ + unsigned char cmd; + unsigned char reg; + unsigned short value; +}; + +struct pmic_otp_prog_t pmic_otp_prog[] = { +WRITE_I2C:7F:01 // Access FSL EXT Page 1 +WRITE_I2C:A0:2B // Auto gen from Row94 +WRITE_I2C:A1:01 // Auto gen from Row95 +WRITE_I2C:A2:05 // Auto gen from Row96 +WRITE_I2C:A8:2B // Auto gen from Row102 +WRITE_I2C:A9:02 // Auto gen from Row103 +WRITE_I2C:AA:01 // Auto gen from Row104 +WRITE_I2C:AC:18 // Auto gen from Row106 +WRITE_I2C:AE:01 // Auto gen from Row108 +WRITE_I2C:B0:2C // Auto gen from Row110 +WRITE_I2C:B1:04 // Auto gen from Row111 +WRITE_I2C:B2:01 // Auto gen from Row112 +WRITE_I2C:B4:2C // Auto gen from Row114 +WRITE_I2C:B5:04 // Auto gen from Row115 +WRITE_I2C:B6:01 // Auto gen from Row116 +WRITE_I2C:B8:18 // Auto gen from Row118 +WRITE_I2C:BA:01 // Auto gen from Row120 +WRITE_I2C:BD:08 // Auto gen from Row123 +WRITE_I2C:C0:06 // Auto gen from Row126 +WRITE_I2C:C4:04 // Auto gen from Row130 +WRITE_I2C:C8:0E // Auto gen from Row134 +WRITE_I2C:CC:0E // Auto gen from Row138 +WRITE_I2C:CD:05 // Auto gen from Row139 +WRITE_I2C:D0:0C // Auto gen from Row142 +WRITE_I2C:D5:07 // Auto gen from Row147 +WRITE_I2C:D8:07 // Auto gen from Row150 +WRITE_I2C:D9:06 // Auto gen from Row151 +WRITE_I2C:DC:0A // Auto gen from Row154 +WRITE_I2C:DD:03 // Auto gen from Row155 +WRITE_I2C:E0:05 // Auto gen from Row158 + +#if 1 /* TBB mode */ +WRITE_I2C:E4:80 // TBB_POR = 1 +DELAY:10 +#else +// Write OTP +WRITE_I2C:E4:02 // FUSE POR1=1 +WRITE_I2C:E5:02 // FUSE POR2=1 +WRITE_I2C:E6:02 // FUSE POR3=1 +WRITE_I2C:F0:1F // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register +WRITE_I2C:F1:1F // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register +WRITE_I2C:7F:02 // Access PF0100 EXT Page2 +WRITE_I2C:D0:1F // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register +WRITE_I2C:D1:1F // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register +//----------------------------------------------------------------------------------- +WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +VPGM:ON // Turn ON 8V SWBST +//VPGM:DOWN:n +//VPGM:UP:n +DELAY:500 // Adds 500msec delay to allow VPGM time to ramp up +//----------------------------------------------------------------------------------- +// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10) +//----------------------------------------------------------------------------------- +// BANK 1 +//----------------------------------------------------------------------------------- +WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F1:03 // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F1:0B // Set Bank 1 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F1:03 // Reset Bank 1 ANTIFUSE_EN +WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 2 +//----------------------------------------------------------------------------------- +WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F2:03 // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F2:0B // Set Bank 2 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F2:03 // Reset Bank 2 ANTIFUSE_EN +WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 3 +//----------------------------------------------------------------------------------- +WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F3:03 // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F3:0B // Set Bank 3 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F3:03 // Reset Bank 3 ANTIFUSE_EN +WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 4 +//----------------------------------------------------------------------------------- +WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F4:03 // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F4:0B // Set Bank 4 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F4:03 // Reset Bank 4 ANTIFUSE_EN +WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 5 +//----------------------------------------------------------------------------------- +WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F5:03 // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F5:0B // Set Bank 5 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F5:03 // Reset Bank 5 ANTIFUSE_EN +WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 6 +//----------------------------------------------------------------------------------- +WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F6:03 // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F6:0B // Set Bank 6 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F6:03 // Reset Bank 6 ANTIFUSE_EN +WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 7 +//----------------------------------------------------------------------------------- +WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F7:03 // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F7:0B // Set Bank 7 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F7:03 // Reset Bank 7 ANTIFUSE_EN +WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 8 +//----------------------------------------------------------------------------------- +WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F8:03 // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F8:0B // Set Bank 8 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F8:03 // Reset Bank 8 ANTIFUSE_EN +WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 9 +//----------------------------------------------------------------------------------- +WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F9:03 // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:F9:0B // Set Bank 9 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:F9:03 // Reset Bank 9 ANTIFUSE_EN +WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 10 +//----------------------------------------------------------------------------------- +WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:FA:03 // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +WRITE_I2C:FA:0B // Set Bank 10 ANTIFUSE_EN +DELAY:10 // Allow time for bank programming to complete +WRITE_I2C:FA:03 // Reset Bank 10 ANTIFUSE_EN +WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +VPGM:OFF // Turn off 8V SWBST +DELAY:500 // Adds delay to allow VPGM to bleed off +WRITE_I2C:D0:00 // Clear +WRITE_I2C:D1:00 // Clear +PWRON:LOW // PWRON LOW to reload new OTP data +DELAY:500 +PWRON: HIGH +#endif +}; \ No newline at end of file diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig new file mode 100644 index 00000000000..20935256a34 --- /dev/null +++ b/configs/colibri_imx6_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_IMX6=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256" diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h new file mode 100644 index 00000000000..174a1de3e41 --- /dev/null +++ b/include/configs/colibri_imx6.h @@ -0,0 +1,325 @@ +/* + * Copyright 2013-2015 Toradex, Inc. + * + * Configuration settings for the Toradex Colibri iMX6 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_MX6 +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET + +#define CONFIG_COLIBRI_IMX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_GENERIC_BOARD + +#include +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MISC_INIT_R + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* Make the HW version stuff available in u-boot env */ +#define CONFIG_VERSION_VARIABLE /* ver environment variable */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* OCOTP Configs */ +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION + +/* Network */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +/* USB Configs */ +/* Host */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#endif /* CONFIG_USB_KEYBOARD */ +/* Client */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_TRDX_VID 0x1B67 +#define CONFIG_TRDX_PID_COLIBRI_IMX6 0x0027 +#define CONFIG_G_DNL_MANUFACTURER "Toradex" +#define CONFIG_G_DNL_VENDOR_NUM CONFIG_TRDX_VID +#define CONFIG_G_DNL_PRODUCT_NUM CONFIG_TRDX_PID_COLIBRI_IMX6 +/* USB DFU */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_CMD_DFU +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (8*1024*1024) + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR +#define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_ELF + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH + +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 1 +#undef CONFIG_IPADDR +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_SERVERIP +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#ifdef CONFIG_CMD_MMC +#define CONFIG_DRIVE_MMC "mmc " +#else +#define CONFIG_DRIVE_MMC +#endif + +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC + +#define DFU_ALT_EMMC_INFO \ + "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "uImage fat 0 1;" \ + "imx6q-colibri-eval-v3.dtb fat 0 1;" \ + "imx6q-colibri-cam-eval-v3.dtb fat 0 1" + +#define EMMC_BOOTCMD \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "emmcboot=run setup; " \ + "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ + "${vidargs}; echo Booting from internal eMMC chip...; " \ + "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ + "${boot_file} && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x12000000\0" \ + "kernel_addr_r=0x10800000\0" \ + "ramdisk_addr_r=0x12100000\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0:on root=/dev/nfs rw netdevwait\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ + "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ + "run nfsdtbload; dhcp ${kernel_addr_r} " \ + "&& bootm ${kernel_addr_r} ${dtbparam}\0" \ + "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ + "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "sdboot=run setup; " \ + "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ + "${vidargs}; echo Booting from SD card in 8bit slot...; " \ + "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ + "${boot_file} && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define USB_BOOTCMD \ + "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ + "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ + "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ + "${boot_file} && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define FDT_FILE "imx6dl-colibri-eval-v3.dtb" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ + "run nfsboot ; echo ; echo nfsboot failed ; " \ + "usb start ;" \ + "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ + "boot_file=uImage\0" \ + "console=ttymxc0\0" \ + "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ + "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ + EMMC_BOOTCMD \ + "fdt_file=" FDT_FILE "\0" \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + "setethupdate=tftpboot ${kernel_addr_r} flash_eth.img\0" \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ + "load ${interface} ${drive}:1 ${kernel_addr_r} flash_blk.img\0" \ + "setup=setenv setupargs fec_mac=${ethaddr} " \ + "consoleblank=0 no_console_suspend=1 console=tty1 " \ + "console=${console},${baudrate}n8\0 " \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate;" \ + " source ${loadaddr}\0" \ + "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ + "load ${interface} ${drive}:1 ${kernel_addr_r} " \ + "flash_blk.img\0" \ + "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \ + "video=mxcfb1:off fbmem=8M\0 " + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Colibri iMX6 # " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 48 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (512 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#define CONFIG_OF_LIBFDT + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_CMD_BMP + +#define CONFIG_CMD_TIME + +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_CMD_FS_GENERIC + +#endif /* __CONFIG_H */ -- cgit v1.2.3