From 77fee01c7c84e888883be17bba0f36c6bbc593e0 Mon Sep 17 00:00:00 2001
From: Max Krummenacher <max.krummenacher@toradex.com>
Date: Tue, 6 May 2014 13:03:46 +0200
Subject: apalis_imx6: changed pad names and setup_sata

follow 10fda48779fc86e74e4482cbc7667431237cf60c
i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents

follow 164d98466103a46b7c881149e92ec2a28a6375be
Move setup_sata to common part
---
 board/toradex/apalis_imx6/apalis_imx6.c | 272 +++++++++++++++-----------------
 board/toradex/apalis_imx6/pf0100.c      |   2 +-
 2 files changed, 129 insertions(+), 145 deletions(-)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index a870075299b..c4afd9fea26 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -19,6 +19,7 @@
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
 #include <asm/imx-common/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -82,14 +83,14 @@ int dram_init(void)
 
 /* Apalis UART1 */
 iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 /* Apalis UART2 */
 iomux_v3_cfg_t const uart2_pads[] = {
-	MX6_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@@ -97,12 +98,12 @@ iomux_v3_cfg_t const uart2_pads[] = {
 struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 		.gp = IMX_GPIO_NR(5, 27)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
+		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 		.gp = IMX_GPIO_NR(5, 26)
 	}
 };
@@ -111,12 +112,12 @@ struct i2c_pads_info i2c_pad_info1 = {
 struct i2c_pads_info i2c_pad_info_loc = {
 	.scl = {
 		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 		.gp = IMX_GPIO_NR(4, 12)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
@@ -125,12 +126,12 @@ struct i2c_pads_info i2c_pad_info_loc = {
 struct i2c_pads_info i2c_pad_info3 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D17__GPIO_3_17 | PC,
+		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
 		.gp = IMX_GPIO_NR(3, 17)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 		.gp = IMX_GPIO_NR(3, 18)
 	}
 };
@@ -139,55 +140,55 @@ struct i2c_pads_info i2c_pad_info3 = {
 struct i2c_pads_info i2c_pad_info_ddc = {
 	.scl = {
 		.i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 		.gp = IMX_GPIO_NR(2, 30)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO_3_16 | PC,
+		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
 		.gp = IMX_GPIO_NR(3, 16)
 	}
 };
 
 /* Apalis MMC1 */
 iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__USDHC1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__USDHC1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_DI0_PIN4__GPIO_4_20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 /* Apalis SD1 */
 iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__USDHC2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__USDHC2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__GPIO_6_14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 /* eMMC */
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__USDHC3_RST   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
 int mx6_rgmii_rework(struct phy_device *phydev)
@@ -222,21 +223,21 @@ int mx6_rgmii_rework(struct phy_device *phydev)
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	/* KSZ9031 PHY Reset */
-	MX6_PAD_ENET_CRS_DV__GPIO_1_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_enet(void)
@@ -252,9 +253,9 @@ static void setup_iomux_enet(void)
 iomux_v3_cfg_t const usb_pads[] = {
 	/* TODO This pin has a dedicated USB power functionality, can we use it? */
 	/* USBH_EN */
-	MX6_PAD_GPIO_0__GPIO_1_0   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_0__GPIO1_IO00  | MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* USB_VBUS_DET */
-	MX6_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_uart(void)
@@ -387,74 +388,55 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#ifdef CONFIG_CMD_SATA
-int setup_sata(void)
-{
-	struct iomuxc_base_regs *const iomuxc_regs
-		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
-	int ret = enable_sata_clock();
-	if (ret)
-		return ret;
-
-	clrsetbits_le32(&iomuxc_regs->gpr[13],
-			IOMUXC_GPR13_SATA_MASK,
-			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
-			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
-			|IOMUXC_GPR13_SATA_SPEED_3G
-			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
-			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
-			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
-			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
-			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
-	return 0;
-}
-#endif
-
 #if defined(CONFIG_VIDEO_IPUV3)
 
 static iomux_v3_cfg_t const backlight_pads[] = {
 	/* Backlight on RGB connector: J15 */
-	MX6_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 /* TODO PWM not GPIO */
-	MX6_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(3, 14)
 	/* PSAVE# integrated VDAC */
-	MX6_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 };
 
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+	/* the bootrom sets the iomux to vselect, potentially connecting
+	 * two outputs. Set this back to GPIO */
+	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
 static iomux_v3_cfg_t const rgb_pads[] = {
 	MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK,
 	MX6_PAD_EIM_DA10__IPU1_DI1_PIN15,
-	MX6_PAD_EIM_DA11__IPU1_DI1_PIN2,
-	MX6_PAD_EIM_DA12__IPU1_DI1_PIN3,
-	MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0,
-	MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1,
-	MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2,
-	MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3,
-	MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4,
-	MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5,
-	MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6,
-	MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7,
-	MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8,
-	MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9,
-	MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10,
-	MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11,
-	MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12,
-	MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13,
-	MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14,
-	MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15,
-	MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16,
-	MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17,
-	MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18,
-	MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19,
-	MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22,
-	MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23,
-	MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21,
-	MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20,
+	MX6_PAD_EIM_DA11__IPU1_DI1_PIN02,
+	MX6_PAD_EIM_DA12__IPU1_DI1_PIN03,
+	MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00,
+	MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01,
+	MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02,
+	MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03,
+	MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04,
+	MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05,
+	MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06,
+	MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07,
+	MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08,
+	MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09,
+	MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10,
+	MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11,
+	MX6_PAD_EIM_A17__IPU1_DISP1_DATA12,
+	MX6_PAD_EIM_A18__IPU1_DISP1_DATA13,
+	MX6_PAD_EIM_A19__IPU1_DISP1_DATA14,
+	MX6_PAD_EIM_A20__IPU1_DISP1_DATA15,
+	MX6_PAD_EIM_A21__IPU1_DISP1_DATA16,
+	MX6_PAD_EIM_A22__IPU1_DISP1_DATA17,
+	MX6_PAD_EIM_A23__IPU1_DISP1_DATA18,
+	MX6_PAD_EIM_A24__IPU1_DISP1_DATA19,
+	MX6_PAD_EIM_D26__IPU1_DISP1_DATA22,
+	MX6_PAD_EIM_D27__IPU1_DISP1_DATA23,
+	MX6_PAD_EIM_D30__IPU1_DISP1_DATA21,
+	MX6_PAD_EIM_D31__IPU1_DISP1_DATA20,
 };
 
 static iomux_v3_cfg_t const vga_pads[] = {
@@ -462,45 +444,45 @@ static iomux_v3_cfg_t const vga_pads[] = {
 	/* Dualite/Solo doesn't have IPU2 */
 	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 #else
 	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 	MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15,
-	MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2,
-	MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3,
-	MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0,
-	MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1,
-	MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2,
-	MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3,
-	MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4,
-	MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5,
-	MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6,
-	MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7,
-	MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8,
-	MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9,
-	MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10,
-	MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11,
-	MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12,
-	MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13,
-	MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14,
-	MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15,
+	MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02,
+	MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03,
+	MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00,
+	MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01,
+	MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02,
+	MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03,
+	MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04,
+	MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05,
+	MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06,
+	MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07,
+	MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08,
+	MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09,
+	MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10,
+	MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11,
+	MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12,
+	MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13,
+	MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14,
+	MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15,
 #endif
 };
 
@@ -772,6 +754,8 @@ static void setup_display(void)
 
 int board_early_init_f(void)
 {
+	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+					ARRAY_SIZE(pwr_intb_pads));
 	setup_iomux_uart();
 
 #if defined(CONFIG_VIDEO_IPUV3)
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
index 1905d142964..116d7b36d05 100644
--- a/board/toradex/apalis_imx6/pf0100.c
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -26,7 +26,7 @@
 #define PFUZE100_I2C_ADDR 		(0x08)
 
 static iomux_v3_cfg_t const pmic_prog_pads[] = {
-	MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 unsigned pmic_init(void)
-- 
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