From 94a16b8e70ba8102d8abb0c9bc64b11e19d4bd55 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:31 +0200 Subject: ARM: socfpga: vining_fpga: Rename VINING|FPGA The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 2 +- arch/arm/mach-socfpga/Kconfig | 10 +- board/samtec/vining_fpga/MAINTAINERS | 5 - board/samtec/vining_fpga/Makefile | 7 - board/samtec/vining_fpga/qts/iocsr_config.h | 659 -------------------------- board/samtec/vining_fpga/qts/pinmux_config.h | 218 --------- board/samtec/vining_fpga/qts/pll_config.h | 90 ---- board/samtec/vining_fpga/qts/sdram_config.h | 343 -------------- board/samtec/vining_fpga/socfpga.c | 93 ---- board/softing/vining_fpga/MAINTAINERS | 5 + board/softing/vining_fpga/Makefile | 7 + board/softing/vining_fpga/qts/iocsr_config.h | 659 ++++++++++++++++++++++++++ board/softing/vining_fpga/qts/pinmux_config.h | 218 +++++++++ board/softing/vining_fpga/qts/pll_config.h | 90 ++++ board/softing/vining_fpga/qts/sdram_config.h | 343 ++++++++++++++ board/softing/vining_fpga/socfpga.c | 93 ++++ configs/socfpga_vining_fpga_defconfig | 6 +- include/configs/socfpga_vining_fpga.h | 12 +- 18 files changed, 1430 insertions(+), 1430 deletions(-) delete mode 100644 board/samtec/vining_fpga/MAINTAINERS delete mode 100644 board/samtec/vining_fpga/Makefile delete mode 100644 board/samtec/vining_fpga/qts/iocsr_config.h delete mode 100644 board/samtec/vining_fpga/qts/pinmux_config.h delete mode 100644 board/samtec/vining_fpga/qts/pll_config.h delete mode 100644 board/samtec/vining_fpga/qts/sdram_config.h delete mode 100644 board/samtec/vining_fpga/socfpga.c create mode 100644 board/softing/vining_fpga/MAINTAINERS create mode 100644 board/softing/vining_fpga/Makefile create mode 100644 board/softing/vining_fpga/qts/iocsr_config.h create mode 100644 board/softing/vining_fpga/qts/pinmux_config.h create mode 100644 board/softing/vining_fpga/qts/pll_config.h create mode 100644 board/softing/vining_fpga/qts/sdram_config.h create mode 100644 board/softing/vining_fpga/socfpga.c diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index ac57f41cb5..be52fbf43d 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -8,7 +8,7 @@ #include / { - model = "samtec VIN|ING FPGA"; + model = "Softing VIN|ING FPGA"; compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 45de153aa5..fc0a54214f 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -100,8 +100,8 @@ config TARGET_SOCFPGA_IS1 bool "IS1 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_SAMTEC_VINING_FPGA - bool "samtec VIN|ING FPGA (Cyclone V)" +config TARGET_SOCFPGA_SOFTING_VINING_FPGA + bool "Softing VIN|ING FPGA (Cyclone V)" select BOARD_LATE_INIT select TARGET_SOCFPGA_CYCLONE5 @@ -145,7 +145,7 @@ config SYS_BOARD default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -155,7 +155,7 @@ config SYS_VENDOR default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES - default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO @@ -178,6 +178,6 @@ config SYS_CONFIG_NAME default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA endif diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/samtec/vining_fpga/MAINTAINERS deleted file mode 100644 index c2002fe3ce..0000000000 --- a/board/samtec/vining_fpga/MAINTAINERS +++ /dev/null @@ -1,5 +0,0 @@ -VINING FPGA BOARD -M: Marek Vasut -S: Maintained -F: include/configs/socfpga_vining_fpga.h -F: configs/socfpga_vining_fpga_defconfig diff --git a/board/samtec/vining_fpga/Makefile b/board/samtec/vining_fpga/Makefile deleted file mode 100644 index e1c8a6b3c7..0000000000 --- a/board/samtec/vining_fpga/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2010, Thomas Chou - -obj-y := socfpga.o diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/samtec/vining_fpga/qts/iocsr_config.h deleted file mode 100644 index 1fe2a09e56..0000000000 --- a/board/samtec/vining_fpga/qts/iocsr_config.h +++ /dev/null @@ -1,659 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA IOCSR configuration - */ - -#ifndef __SOCFPGA_IOCSR_CONFIG_H__ -#define __SOCFPGA_IOCSR_CONFIG_H__ - -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 - -const unsigned long iocsr_scan_chain0_table[] = { - 0x00000000, - 0x00000000, - 0x0FF00000, - 0xC0000000, - 0x0000003F, - 0x00008000, - 0x00060180, - 0x18060000, - 0x18000000, - 0x00018060, - 0x00000000, - 0x00004000, - 0x000300C0, - 0x0C030000, - 0x0C000000, - 0x00000030, - 0x0000C030, - 0x00002000, - 0x00018060, - 0x06018000, - 0x06000000, - 0x00000018, - 0x00006018, - 0x00001000, -}; - -const unsigned long iocsr_scan_chain1_table[] = { - 0x00000000, - 0x300C0000, - 0x000000C0, - 0x00000000, - 0x00000000, - 0x00008000, - 0x00060180, - 0x18060000, - 0x18000000, - 0x00000060, - 0x00018060, - 0x00004000, - 0x000300C0, - 0x0C030000, - 0x0C000000, - 0x00000030, - 0x0000C030, - 0x00002000, - 0x06018060, - 0x06018000, - 0x01FE0000, - 0xF8000000, - 0x00000007, - 0x00001000, - 0x0000C030, - 0x0300C000, - 0x03000000, - 0x0000300C, - 0x0000300C, - 0x00000800, - 0x00000000, - 0x00000000, - 0x01800000, - 0x00000006, - 0x00601806, - 0x00000400, - 0x00000000, - 0x00C03000, - 0x00000003, - 0x00000000, - 0x00000000, - 0x00000200, - 0x00601806, - 0x00000000, - 0x80600000, - 0x80000601, - 0x00000601, - 0x00000100, - 0x00300C03, - 0xC0300C00, - 0xC0300000, - 0xC0000300, - 0x000C0300, - 0x00000080, -}; - -const unsigned long iocsr_scan_chain2_table[] = { - 0x300C0300, - 0x300C0000, - 0x0FF00000, - 0x00000000, - 0x000300C0, - 0x00008000, - 0x18060180, - 0x18060000, - 0x00000000, - 0x00000000, - 0x00018060, - 0x00004000, - 0x000300C0, - 0x0C030000, - 0x00000030, - 0x00000000, - 0x0300C030, - 0x00002000, - 0x00018060, - 0x06018000, - 0x06000000, - 0x00000018, - 0x00006018, - 0x00001000, - 0x0000C030, - 0x00000000, - 0x03000000, - 0x0000000C, - 0x00C0300C, - 0x00000800, -}; - -const unsigned long iocsr_scan_chain3_table[] = { - 0x0C420D80, - 0x082000FF, - 0x0A804001, - 0x07900000, - 0x08020000, - 0x00100000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, - 0x00000000, - 0x00000021, - 0x82000004, - 0x05400000, - 0x03C80000, - 0x04010000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0xE4400000, - 0x00001800, - 0x00600391, - 0x800E4400, - 0x00000001, - 0x40000002, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000010, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0x40680A28, - 0x41034051, - 0x12481A00, - 0x80A280D0, - 0x34051406, - 0x01A02490, - 0x080D0000, - 0x51406802, - 0x02490340, - 0xD000001A, - 0x0680A280, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, - 0x007F8006, - 0x00000000, - 0x0A800001, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, - 0x00000FF0, - 0x72200000, - 0x80000C00, - 0x05400000, - 0x02480000, - 0x04000000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0x6A1C0000, - 0x00001800, - 0x00600391, - 0x800E4400, - 0x1A870001, - 0x40000600, - 0x02A00040, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000010, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0x40680208, - 0x49034051, - 0x12481A02, - 0x80A280D0, - 0x34030C06, - 0x01A00040, - 0x280D0002, - 0x5140680A, - 0x02490340, - 0xD012481A, - 0x0680A280, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, - 0x007F8006, - 0x00000000, - 0x99300001, - 0x34343400, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x01000000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0xC880090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0x8A28A3D5, - 0xF6D1451E, - 0x034AD348, - 0x821A0000, - 0x0000D000, - 0x05140680, - 0xD569A47A, - 0x1E8A28A3, - 0x48F6D145, - 0x00035292, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x00003FC2, - 0x00820000, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00015000, - 0x0000F200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00600391, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0x8A28A3D5, - 0xF4D1451E, - 0x034AD348, - 0x821A0186, - 0x0000D000, - 0x00000680, - 0xD569A47A, - 0x1EF228A3, - 0x48F4D145, - 0x00034AD3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0xC880090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, - 0x00D00000, - 0x0C864000, - 0x59647A03, - 0xCB2CA3DD, - 0xF6D9651E, - 0x034AD348, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xDD59647A, - 0x1E8A28A3, - 0x48F6D965, - 0x00034AD3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00400000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F16080, - 0x1A041404, - 0x00D00000, - 0x04864000, - 0x69A47A01, - 0xF228A3D5, - 0xF4D1451E, - 0x03529248, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD559647A, - 0x1E8A28A3, - 0x48F6D145, - 0x00034AD3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0x00489800, - 0x801A1A1A, - 0x00000200, - 0x80000004, - 0x00000200, - 0x80000004, - 0x00000200, - 0x80000004, - 0x00000200, - 0x00000004, - 0x00040000, - 0x10000000, - 0x00000000, - 0x00000040, - 0x00010000, - 0x40002000, - 0x00000100, - 0x40000002, - 0x00000100, - 0x40000002, - 0x00000100, - 0x40000002, - 0x00000100, - 0x00000002, - 0x00020000, - 0x08000000, - 0x00000000, - 0x00000020, - 0x00008000, - 0x20001000, - 0x00000080, - 0x20000001, - 0x00000080, - 0x20000001, - 0x00000080, - 0x20000001, - 0x00000080, - 0x00000001, - 0x00010000, - 0x04000000, - 0x00FF0000, - 0x00000000, - 0x00004000, - 0x00000800, - 0xC0000001, - 0x00041419, - 0x40000000, - 0x04000816, - 0x000D0000, - 0x00006800, - 0x00000340, - 0xD000001A, - 0x06800000, - 0x00340000, - 0x0001A000, - 0x00000D00, - 0x40000068, - 0x1A000003, - 0x00D00000, - 0x00068000, - 0x00003400, - 0x000001A0, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000401, - 0x80000008, - 0x0000007F, - 0x20000000, - 0x00000000, - 0xE0000080, - 0x0000001F, - 0x00004000, -}; - - -#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/samtec/vining_fpga/qts/pinmux_config.h deleted file mode 100644 index 40b89123ec..0000000000 --- a/board/samtec/vining_fpga/qts/pinmux_config.h +++ /dev/null @@ -1,218 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA PinMux configuration - */ - -#ifndef __SOCFPGA_PINMUX_CONFIG_H__ -#define __SOCFPGA_PINMUX_CONFIG_H__ - -const u8 sys_mgr_init_table[] = { - 0, /* EMACIO0 */ - 2, /* EMACIO1 */ - 2, /* EMACIO2 */ - 2, /* EMACIO3 */ - 2, /* EMACIO4 */ - 2, /* EMACIO5 */ - 2, /* EMACIO6 */ - 2, /* EMACIO7 */ - 2, /* EMACIO8 */ - 0, /* EMACIO9 */ - 2, /* EMACIO10 */ - 2, /* EMACIO11 */ - 2, /* EMACIO12 */ - 2, /* EMACIO13 */ - 0, /* EMACIO14 */ - 0, /* EMACIO15 */ - 0, /* EMACIO16 */ - 0, /* EMACIO17 */ - 0, /* EMACIO18 */ - 0, /* EMACIO19 */ - 2, /* FLASHIO0 */ - 2, /* FLASHIO1 */ - 2, /* FLASHIO2 */ - 2, /* FLASHIO3 */ - 2, /* FLASHIO4 */ - 2, /* FLASHIO5 */ - 2, /* FLASHIO6 */ - 2, /* FLASHIO7 */ - 2, /* FLASHIO8 */ - 2, /* FLASHIO9 */ - 2, /* FLASHIO10 */ - 2, /* FLASHIO11 */ - 0, /* GENERALIO0 */ - 1, /* GENERALIO1 */ - 1, /* GENERALIO2 */ - 1, /* GENERALIO3 */ - 1, /* GENERALIO4 */ - 0, /* GENERALIO5 */ - 0, /* GENERALIO6 */ - 1, /* GENERALIO7 */ - 1, /* GENERALIO8 */ - 3, /* GENERALIO9 */ - 3, /* GENERALIO10 */ - 3, /* GENERALIO11 */ - 3, /* GENERALIO12 */ - 0, /* GENERALIO13 */ - 0, /* GENERALIO14 */ - 2, /* GENERALIO15 */ - 2, /* GENERALIO16 */ - 0, /* GENERALIO17 */ - 0, /* GENERALIO18 */ - 0, /* GENERALIO19 */ - 0, /* GENERALIO20 */ - 0, /* GENERALIO21 */ - 0, /* GENERALIO22 */ - 0, /* GENERALIO23 */ - 0, /* GENERALIO24 */ - 0, /* GENERALIO25 */ - 0, /* GENERALIO26 */ - 0, /* GENERALIO27 */ - 0, /* GENERALIO28 */ - 0, /* GENERALIO29 */ - 0, /* GENERALIO30 */ - 0, /* GENERALIO31 */ - 2, /* MIXED1IO0 */ - 2, /* MIXED1IO1 */ - 2, /* MIXED1IO2 */ - 2, /* MIXED1IO3 */ - 2, /* MIXED1IO4 */ - 2, /* MIXED1IO5 */ - 2, /* MIXED1IO6 */ - 2, /* MIXED1IO7 */ - 2, /* MIXED1IO8 */ - 2, /* MIXED1IO9 */ - 2, /* MIXED1IO10 */ - 2, /* MIXED1IO11 */ - 2, /* MIXED1IO12 */ - 2, /* MIXED1IO13 */ - 2, /* MIXED1IO14 */ - 3, /* MIXED1IO15 */ - 3, /* MIXED1IO16 */ - 3, /* MIXED1IO17 */ - 3, /* MIXED1IO18 */ - 3, /* MIXED1IO19 */ - 3, /* MIXED1IO20 */ - 0, /* MIXED1IO21 */ - 0, /* MIXED2IO0 */ - 0, /* MIXED2IO1 */ - 0, /* MIXED2IO2 */ - 0, /* MIXED2IO3 */ - 0, /* MIXED2IO4 */ - 0, /* MIXED2IO5 */ - 0, /* MIXED2IO6 */ - 0, /* MIXED2IO7 */ - 0, /* GPLINMUX48 */ - 0, /* GPLINMUX49 */ - 0, /* GPLINMUX50 */ - 0, /* GPLINMUX51 */ - 0, /* GPLINMUX52 */ - 0, /* GPLINMUX53 */ - 0, /* GPLINMUX54 */ - 0, /* GPLINMUX55 */ - 0, /* GPLINMUX56 */ - 0, /* GPLINMUX57 */ - 0, /* GPLINMUX58 */ - 0, /* GPLINMUX59 */ - 0, /* GPLINMUX60 */ - 0, /* GPLINMUX61 */ - 0, /* GPLINMUX62 */ - 0, /* GPLINMUX63 */ - 0, /* GPLINMUX64 */ - 0, /* GPLINMUX65 */ - 0, /* GPLINMUX66 */ - 0, /* GPLINMUX67 */ - 0, /* GPLINMUX68 */ - 0, /* GPLINMUX69 */ - 0, /* GPLINMUX70 */ - 1, /* GPLMUX0 */ - 1, /* GPLMUX1 */ - 1, /* GPLMUX2 */ - 1, /* GPLMUX3 */ - 1, /* GPLMUX4 */ - 1, /* GPLMUX5 */ - 1, /* GPLMUX6 */ - 1, /* GPLMUX7 */ - 1, /* GPLMUX8 */ - 1, /* GPLMUX9 */ - 1, /* GPLMUX10 */ - 1, /* GPLMUX11 */ - 1, /* GPLMUX12 */ - 1, /* GPLMUX13 */ - 1, /* GPLMUX14 */ - 1, /* GPLMUX15 */ - 1, /* GPLMUX16 */ - 1, /* GPLMUX17 */ - 1, /* GPLMUX18 */ - 1, /* GPLMUX19 */ - 1, /* GPLMUX20 */ - 1, /* GPLMUX21 */ - 1, /* GPLMUX22 */ - 1, /* GPLMUX23 */ - 1, /* GPLMUX24 */ - 1, /* GPLMUX25 */ - 1, /* GPLMUX26 */ - 1, /* GPLMUX27 */ - 1, /* GPLMUX28 */ - 1, /* GPLMUX29 */ - 1, /* GPLMUX30 */ - 1, /* GPLMUX31 */ - 1, /* GPLMUX32 */ - 1, /* GPLMUX33 */ - 1, /* GPLMUX34 */ - 1, /* GPLMUX35 */ - 1, /* GPLMUX36 */ - 1, /* GPLMUX37 */ - 1, /* GPLMUX38 */ - 1, /* GPLMUX39 */ - 1, /* GPLMUX40 */ - 1, /* GPLMUX41 */ - 1, /* GPLMUX42 */ - 1, /* GPLMUX43 */ - 1, /* GPLMUX44 */ - 1, /* GPLMUX45 */ - 1, /* GPLMUX46 */ - 1, /* GPLMUX47 */ - 1, /* GPLMUX48 */ - 1, /* GPLMUX49 */ - 1, /* GPLMUX50 */ - 1, /* GPLMUX51 */ - 1, /* GPLMUX52 */ - 1, /* GPLMUX53 */ - 1, /* GPLMUX54 */ - 1, /* GPLMUX55 */ - 1, /* GPLMUX56 */ - 1, /* GPLMUX57 */ - 1, /* GPLMUX58 */ - 1, /* GPLMUX59 */ - 1, /* GPLMUX60 */ - 1, /* GPLMUX61 */ - 1, /* GPLMUX62 */ - 1, /* GPLMUX63 */ - 1, /* GPLMUX64 */ - 1, /* GPLMUX65 */ - 1, /* GPLMUX66 */ - 1, /* GPLMUX67 */ - 1, /* GPLMUX68 */ - 1, /* GPLMUX69 */ - 1, /* GPLMUX70 */ - 0, /* NANDUSEFPGA */ - 0, /* UART0USEFPGA */ - 0, /* RGMII1USEFPGA */ - 1, /* SPIS0USEFPGA */ - 0, /* CAN0USEFPGA */ - 0, /* I2C0USEFPGA */ - 0, /* SDMMCUSEFPGA */ - 0, /* QSPIUSEFPGA */ - 1, /* SPIS1USEFPGA */ - 1, /* RGMII0USEFPGA */ - 0, /* UART1USEFPGA */ - 0, /* CAN1USEFPGA */ - 0, /* USB1USEFPGA */ - 0, /* I2C3USEFPGA */ - 0, /* I2C2USEFPGA */ - 0, /* I2C1USEFPGA */ - 0, /* SPIM1USEFPGA */ - 0, /* USB0USEFPGA */ - 0 /* SPIM0USEFPGA */ -}; -#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/samtec/vining_fpga/qts/pll_config.h deleted file mode 100644 index 5d2a08ba00..0000000000 --- a/board/samtec/vining_fpga/qts/pll_config.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA Clock and PLL configuration - */ - -#ifndef __SOCFPGA_PLL_CONFIG_H__ -#define __SOCFPGA_PLL_CONFIG_H__ - -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 - -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 - -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 - -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 - -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 488281 -#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 - -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 - - -#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h deleted file mode 100644 index de9f0e4153..0000000000 --- a/board/samtec/vining_fpga/qts/sdram_config.h +++ /dev/null @@ -1,343 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA SDRAM configuration - */ - -#ifndef __SOCFPGA_SDRAM_CONFIG_H__ -#define __SOCFPGA_SDRAM_CONFIG_H__ - -/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 - -/* Sequencer auto configuration */ -#define RW_MGR_ACTIVATE_0_AND_1 0x0D -#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E -#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 -#define RW_MGR_ACTIVATE_1 0x0F -#define RW_MGR_CLEAR_DQS_ENABLE 0x49 -#define RW_MGR_GUARANTEED_READ 0x4C -#define RW_MGR_GUARANTEED_READ_CONT 0x54 -#define RW_MGR_GUARANTEED_WRITE 0x18 -#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B -#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F -#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 -#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D -#define RW_MGR_IDLE 0x00 -#define RW_MGR_IDLE_LOOP1 0x7B -#define RW_MGR_IDLE_LOOP2 0x7A -#define RW_MGR_INIT_RESET_0_CKE_0 0x6F -#define RW_MGR_INIT_RESET_1_CKE_0 0x74 -#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 -#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 -#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 -#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 -#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 -#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 -#define RW_MGR_MRS0_DLL_RESET 0x02 -#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 -#define RW_MGR_MRS0_USER 0x07 -#define RW_MGR_MRS0_USER_MIRR 0x0C -#define RW_MGR_MRS1 0x03 -#define RW_MGR_MRS1_MIRR 0x09 -#define RW_MGR_MRS2 0x04 -#define RW_MGR_MRS2_MIRR 0x0A -#define RW_MGR_MRS3 0x05 -#define RW_MGR_MRS3_MIRR 0x0B -#define RW_MGR_PRECHARGE_ALL 0x12 -#define RW_MGR_READ_B2B 0x59 -#define RW_MGR_READ_B2B_WAIT1 0x61 -#define RW_MGR_READ_B2B_WAIT2 0x6B -#define RW_MGR_REFRESH_ALL 0x14 -#define RW_MGR_RETURN 0x01 -#define RW_MGR_SGLE_READ 0x7D -#define RW_MGR_ZQCL 0x06 - -/* Sequencer defines configuration */ -#define AFI_RATE_RATIO 1 -#define CALIB_LFIFO_OFFSET 7 -#define CALIB_VFIFO_OFFSET 5 -#define ENABLE_SUPER_QUICK_CALIBRATION 0 -#define IO_DELAY_PER_DCHAIN_TAP 25 -#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#define IO_DELAY_PER_OPA_TAP 312 -#define IO_DLL_CHAIN_LENGTH 8 -#define IO_DQDQS_OUT_PHASE_MAX 0 -#define IO_DQS_EN_DELAY_MAX 31 -#define IO_DQS_EN_DELAY_OFFSET 0 -#define IO_DQS_EN_PHASE_MAX 7 -#define IO_DQS_IN_DELAY_MAX 31 -#define IO_DQS_IN_RESERVE 4 -#define IO_DQS_OUT_RESERVE 4 -#define IO_IO_IN_DELAY_MAX 31 -#define IO_IO_OUT1_DELAY_MAX 31 -#define IO_IO_OUT2_DELAY_MAX 0 -#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 -#define MAX_LATENCY_COUNT_WIDTH 5 -#define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c -#define RW_MGR_MEM_ADDRESS_MIRRORING 0 -#define RW_MGR_MEM_DATA_MASK_WIDTH 4 -#define RW_MGR_MEM_DATA_WIDTH 32 -#define RW_MGR_MEM_DQ_PER_READ_DQS 8 -#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 -#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 -#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 -#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 -#define RW_MGR_MEM_NUMBER_OF_RANKS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 -#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 -#define TINIT_CNTR0_VAL 99 -#define TINIT_CNTR1_VAL 32 -#define TINIT_CNTR2_VAL 32 -#define TRESET_CNTR0_VAL 99 -#define TRESET_CNTR1_VAL 99 -#define TRESET_CNTR2_VAL 10 - -/* Sequencer ac_rom_init configuration */ -const u32 ac_rom_init[] = { - 0x20700000, - 0x20780000, - 0x10080421, - 0x10080520, - 0x10090046, - 0x100a0088, - 0x100b0000, - 0x10380400, - 0x10080441, - 0x100804c0, - 0x100a0026, - 0x10090110, - 0x100b0000, - 0x30780000, - 0x38780000, - 0x30780000, - 0x10680000, - 0x106b0000, - 0x10280400, - 0x10480000, - 0x1c980000, - 0x1c9b0000, - 0x1c980008, - 0x1c9b0008, - 0x38f80000, - 0x3cf80000, - 0x38780000, - 0x18180000, - 0x18980000, - 0x13580000, - 0x135b0000, - 0x13580008, - 0x135b0008, - 0x33780000, - 0x10580008, - 0x10780000 -}; - -/* Sequencer inst_rom_init configuration */ -const u32 inst_rom_init[] = { - 0x80000, - 0x80680, - 0x8180, - 0x8200, - 0x8280, - 0x8300, - 0x8380, - 0x8100, - 0x8480, - 0x8500, - 0x8580, - 0x8600, - 0x8400, - 0x800, - 0x8680, - 0x880, - 0xa680, - 0x80680, - 0x900, - 0x80680, - 0x980, - 0xa680, - 0x8680, - 0x80680, - 0xb68, - 0xcce8, - 0xae8, - 0x8ce8, - 0xb88, - 0xec88, - 0xa08, - 0xac88, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x60e80, - 0x61080, - 0x61080, - 0x61080, - 0xa680, - 0x8680, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x70e80, - 0x71080, - 0x71080, - 0x71080, - 0xa680, - 0x8680, - 0x80680, - 0x1158, - 0x6d8, - 0x80680, - 0x1168, - 0x7e8, - 0x7e8, - 0x87e8, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x1168, - 0x7e8, - 0x7e8, - 0xa7e8, - 0x80680, - 0x40e88, - 0x41088, - 0x41088, - 0x41088, - 0x40f68, - 0x410e8, - 0x410e8, - 0x410e8, - 0xa680, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x41008, - 0x41088, - 0x41088, - 0x41088, - 0x1100, - 0xc680, - 0x8680, - 0xe680, - 0x80680, - 0x0, - 0x8000, - 0xa000, - 0xc000, - 0x80000, - 0x80, - 0x8080, - 0xa080, - 0xc080, - 0x80080, - 0x9180, - 0x8680, - 0xa680, - 0x80680, - 0x40f08, - 0x80680 -}; - -#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c deleted file mode 100644 index 1e095a4e7d..0000000000 --- a/board/samtec/vining_fpga/socfpga.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Altera Corporation - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ -int board_late_init(void) -{ - const unsigned int phy_nrst_gpio = 0; - const unsigned int usb_nrst_gpio = 35; - int ret; - - status_led_set(1, CONFIG_LED_STATUS_ON); - status_led_set(2, CONFIG_LED_STATUS_ON); - - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); - if (!ret) - gpio_direction_output(phy_nrst_gpio, 1); - else - printf("Cannot remove PHY from reset!\n"); - - ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); - if (!ret) - gpio_direction_output(usb_nrst_gpio, 1); - else - printf("Cannot remove USB from reset!\n"); - - mdelay(50); - - return 0; -} - -#ifndef CONFIG_SPL_BUILD -int misc_init_r(void) -{ - uchar data[128]; - char str[32]; - u32 serial; - int ret; - - /* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */ - ret = eeprom_read(0x50, 0, data, sizeof(data)); - if (ret) { - puts("Cannot read I2C EEPROM.\n"); - return 0; - } - - /* Check EEPROM signature. */ - if (!(data[0] == 0xa5 && data[1] == 0x5a)) { - puts("Invalid I2C EEPROM signature.\n"); - env_set("unit_serial", "invalid"); - env_set("unit_ident", "VINing-xxxx-STD"); - env_set("hostname", "vining-invalid"); - return 0; - } - - /* If 'unit_serial' is already set, do nothing. */ - if (!env_get("unit_serial")) { - /* This field is Big Endian ! */ - serial = (data[0x54] << 24) | (data[0x55] << 16) | - (data[0x56] << 8) | (data[0x57] << 0); - memset(str, 0, sizeof(str)); - sprintf(str, "%07i", serial); - env_set("unit_serial", str); - } - - if (!env_get("unit_ident")) { - memset(str, 0, sizeof(str)); - memcpy(str, &data[0x2e], 18); - env_set("unit_ident", str); - } - - /* Set ethernet address from EEPROM. */ - if (!env_get("ethaddr") && is_valid_ethaddr(&data[0x62])) - eth_env_set_enetaddr("ethaddr", &data[0x62]); - - return 0; -} -#endif diff --git a/board/softing/vining_fpga/MAINTAINERS b/board/softing/vining_fpga/MAINTAINERS new file mode 100644 index 0000000000..c2002fe3ce --- /dev/null +++ b/board/softing/vining_fpga/MAINTAINERS @@ -0,0 +1,5 @@ +VINING FPGA BOARD +M: Marek Vasut +S: Maintained +F: include/configs/socfpga_vining_fpga.h +F: configs/socfpga_vining_fpga_defconfig diff --git a/board/softing/vining_fpga/Makefile b/board/softing/vining_fpga/Makefile new file mode 100644 index 0000000000..e1c8a6b3c7 --- /dev/null +++ b/board/softing/vining_fpga/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou + +obj-y := socfpga.o diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h new file mode 100644 index 0000000000..1fe2a09e56 --- /dev/null +++ b/board/softing/vining_fpga/qts/iocsr_config.h @@ -0,0 +1,659 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00000000, + 0x300C0000, + 0x000000C0, + 0x00000000, + 0x00000000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00601806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x300C0000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x00000000, + 0x00000000, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680A28, + 0x41034051, + 0x12481A00, + 0x80A280D0, + 0x34051406, + 0x01A02490, + 0x080D0000, + 0x51406802, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x5140680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF6D1451E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD569A47A, + 0x1E8A28A3, + 0x48F6D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF4D1451E, + 0x034AD348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xD569A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xCB2CA3DD, + 0xF6D9651E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1E8A28A3, + 0x48F6D965, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F16080, + 0x1A041404, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xF228A3D5, + 0xF4D1451E, + 0x03529248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8A28A3, + 0x48F6D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/softing/vining_fpga/qts/pinmux_config.h b/board/softing/vining_fpga/qts/pinmux_config.h new file mode 100644 index 0000000000..40b89123ec --- /dev/null +++ b/board/softing/vining_fpga/qts/pinmux_config.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 2, /* FLASHIO0 */ + 2, /* FLASHIO1 */ + 2, /* FLASHIO2 */ + 2, /* FLASHIO3 */ + 2, /* FLASHIO4 */ + 2, /* FLASHIO5 */ + 2, /* FLASHIO6 */ + 2, /* FLASHIO7 */ + 2, /* FLASHIO8 */ + 2, /* FLASHIO9 */ + 2, /* FLASHIO10 */ + 2, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 2, /* GENERALIO15 */ + 2, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 2, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 1, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 1, /* SPIS1USEFPGA */ + 1, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h new file mode 100644 index 0000000000..5d2a08ba00 --- /dev/null +++ b/board/softing/vining_fpga/qts/pll_config.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 488281 +#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h new file mode 100644 index 0000000000..de9f0e4153 --- /dev/null +++ b/board/softing/vining_fpga/qts/sdram_config.h @@ -0,0 +1,343 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA SDRAM configuration + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080421, + 0x10080520, + 0x10090046, + 0x100a0088, + 0x100b0000, + 0x10380400, + 0x10080441, + 0x100804c0, + 0x100a0026, + 0x10090110, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c new file mode 100644 index 0000000000..1e095a4e7d --- /dev/null +++ b/board/softing/vining_fpga/socfpga.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Altera Corporation + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_late_init(void) +{ + const unsigned int phy_nrst_gpio = 0; + const unsigned int usb_nrst_gpio = 35; + int ret; + + status_led_set(1, CONFIG_LED_STATUS_ON); + status_led_set(2, CONFIG_LED_STATUS_ON); + + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); + if (!ret) + gpio_direction_output(phy_nrst_gpio, 1); + else + printf("Cannot remove PHY from reset!\n"); + + ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); + if (!ret) + gpio_direction_output(usb_nrst_gpio, 1); + else + printf("Cannot remove USB from reset!\n"); + + mdelay(50); + + return 0; +} + +#ifndef CONFIG_SPL_BUILD +int misc_init_r(void) +{ + uchar data[128]; + char str[32]; + u32 serial; + int ret; + + /* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */ + ret = eeprom_read(0x50, 0, data, sizeof(data)); + if (ret) { + puts("Cannot read I2C EEPROM.\n"); + return 0; + } + + /* Check EEPROM signature. */ + if (!(data[0] == 0xa5 && data[1] == 0x5a)) { + puts("Invalid I2C EEPROM signature.\n"); + env_set("unit_serial", "invalid"); + env_set("unit_ident", "VINing-xxxx-STD"); + env_set("hostname", "vining-invalid"); + return 0; + } + + /* If 'unit_serial' is already set, do nothing. */ + if (!env_get("unit_serial")) { + /* This field is Big Endian ! */ + serial = (data[0x54] << 24) | (data[0x55] << 16) | + (data[0x56] << 8) | (data[0x57] << 0); + memset(str, 0, sizeof(str)); + sprintf(str, "%07i", serial); + env_set("unit_serial", str); + } + + if (!env_get("unit_ident")) { + memset(str, 0, sizeof(str)); + memcpy(str, &data[0x2e], 18); + env_set("unit_ident", str); + } + + /* Set ethernet address from EEPROM. */ + if (!env_get("ethaddr") && is_valid_ethaddr(&data[0x62])) + eth_env_set_enetaddr("ethaddr", &data[0x62]); + + return 0; +} +#endif diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index c52afddd20..faa4a17de5 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y +CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -35,7 +35,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set @@ -86,7 +86,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="samtec" +CONFIG_USB_GADGET_MANUFACTURER="softing" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 232536a763..ef3221e1c8 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2015 Marek Vasut + * Copyright (C) 2015-2019 Marek Vasut */ -#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__ -#define __CONFIG_SAMTEC_VINING_FPGA_H__ +#ifndef __CONFIG_SOFTING_VINING_FPGA_H__ +#define __CONFIG_SOFTING_VINING_FPGA_H__ #include @@ -50,8 +50,8 @@ "1m(u-boot)," \ "64k(env1)," \ "64k(env2)," \ - "256k(samtec1)," \ - "256k(samtec2)," \ + "256k(softing1)," \ + "256k(softing2)," \ "-(rcvrfs)\0" /* Recovery */ \ "mtdparts_1=ff705000.spi.1:" \ "32m(rootfs)," \ @@ -150,4 +150,4 @@ /* The rest of the configuration is shared */ #include -#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */ +#endif /* __CONFIG_SOFTING_VINING_FPGA_H__ */ -- cgit v1.2.3 From 4a9f633e3d13dbeb6a88de13074c48ec63210f5c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:32 +0200 Subject: ARM: socfpga: vining_fpga: Update DT Pick minor changes from the downstream DT, disable MMC, add GMAC0 node and adjust PHY skew settings for GMAC1. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 15 ++++++++++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index db55a4ecad..44bedd8b67 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -20,7 +20,7 @@ }; &mmc { - u-boot,dm-pre-reloc; + status = "disabled"; }; &qspi { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index be52fbf43d..3fb6e14372 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR X11) /* - * Copyright (C) 2015 Marek Vasut + * Copyright (C) 2015-2019 Marek Vasut */ #include "socfpga_cyclone5.dtsi" @@ -65,6 +65,11 @@ }; }; +&gmac0 { + status = "disabled"; + phy-mode = "gmii"; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; @@ -84,10 +89,14 @@ rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <1560>; + txc-skew-ps = <1860>; rxdv-skew-ps = <0>; - rxc-skew-ps = <1200>; + rxc-skew-ps = <1860>; }; }; }; -- cgit v1.2.3 From 76f0f010086aad0847e846633688262655c4a9d4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:33 +0200 Subject: ARM: socfpga: vining_fpga: Update generated headers Update headers generated by quartus to the latest version. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- board/softing/vining_fpga/qts/iocsr_config.h | 140 +++++++++++++------------- board/softing/vining_fpga/qts/pinmux_config.h | 6 +- board/softing/vining_fpga/qts/pll_config.h | 12 +-- board/softing/vining_fpga/qts/sdram_config.h | 12 +-- 4 files changed, 82 insertions(+), 88 deletions(-) diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h index 1fe2a09e56..8c78aecdd3 100644 --- a/board/softing/vining_fpga/qts/iocsr_config.h +++ b/board/softing/vining_fpga/qts/iocsr_config.h @@ -139,9 +139,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x07900000, 0x08020000, 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, + 0xD4380000, + 0xE0003000, + 0x00C00350, 0x00000000, 0x00000021, 0x82000004, @@ -153,10 +153,10 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x03C80000, 0x05400000, 0x03C80000, - 0xE4400000, - 0x00001800, - 0x00600391, - 0x800E4400, + 0x6A1C0000, + 0x70001800, + 0x006001A8, + 0x8006A1C0, 0x00000001, 0x40000002, 0x02A00000, @@ -167,11 +167,11 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x01E40000, 0x02A00000, 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, + 0x350E0000, + 0x38000C00, + 0x003000D4, + 0xC00350E0, + 0x0D438000, 0x20000300, 0x00040000, 0x50670000, @@ -200,9 +200,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x15000000, 0x0F200000, 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, + 0xC0000000, + 0x018006A1, + 0x001A8700, 0x007F8006, 0x00000000, 0x0A800001, @@ -213,11 +213,11 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x07900000, 0x08020000, 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, + 0xD4380000, + 0xE0003000, + 0x00C00350, 0x00000FF0, - 0x72200000, + 0x350E0000, 0x80000C00, 0x05400000, 0x02480000, @@ -228,9 +228,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x05400000, 0x03C80000, 0x6A1C0000, - 0x00001800, - 0x00600391, - 0x800E4400, + 0x70001800, + 0x006001A8, + 0x8006A1C0, 0x1A870001, 0x40000600, 0x02A00040, @@ -241,11 +241,11 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x01E40000, 0x02A00000, 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, + 0x350E0000, + 0x38000C00, + 0x003000D4, + 0xC00350E0, + 0x0D438000, 0x20000300, 0x00040000, 0x50670000, @@ -262,9 +262,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x01A00040, 0x280D0002, 0x5140680A, - 0x02490340, - 0xD012481A, - 0x0680A280, + 0x01450340, + 0xD00A281A, + 0x0680E380, 0x10040000, 0x00200000, 0x10040000, @@ -274,9 +274,9 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x15000000, 0x0F200000, 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, + 0xC0000000, + 0x018006A1, + 0x001A8700, 0x007F8006, 0x00000000, 0x99300001, @@ -304,8 +304,8 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x5506A000, 0x00E1D400, 0x00000000, - 0xC880090C, - 0x00003001, + 0xD438090C, + 0x00003000, 0x90400000, 0x00000000, 0x2020C243, @@ -325,22 +325,22 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, 0x00D00000, 0x14864000, 0x59647A05, - 0x8A28A3D5, + 0x8A28A3DD, 0xF6D1451E, 0x034AD348, 0x821A0000, 0x0000D000, 0x05140680, - 0xD569A47A, + 0xDD59647A, 0x1E8A28A3, 0x48F6D145, - 0x00035292, + 0x00034AD3, 0x00080200, 0x00001000, 0x00080200, @@ -393,27 +393,27 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x0000F200, 0x00000000, 0x00000482, - 0x00120800, - 0x00600391, + 0x70120800, + 0x006001A8, 0x80000000, 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, 0x00D00000, 0x14864000, 0x59647A05, - 0x8A28A3D5, - 0xF4D1451E, + 0x8A28A3DD, + 0xF6D1451E, 0x034AD348, 0x821A0186, 0x0000D000, 0x00000680, - 0xD569A47A, - 0x1EF228A3, - 0x48F4D145, + 0xDD59647A, + 0x1E8A28A3, + 0x48F6D145, 0x00034AD3, 0x00080200, 0x00001000, @@ -452,8 +452,8 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x5506A000, 0x00E1D400, 0x00000000, - 0xC880090C, - 0x00003001, + 0xD438090C, + 0x00003000, 0x90400000, 0x00000000, 0x2020C243, @@ -473,21 +473,21 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F36080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, 0x00D00000, - 0x0C864000, - 0x59647A03, - 0xCB2CA3DD, - 0xF6D9651E, + 0x14864000, + 0x59647A05, + 0x8A28A3DD, + 0xF6D1451E, 0x034AD348, 0x821A0000, 0x0000D000, 0x00000680, 0xDD59647A, 0x1E8A28A3, - 0x48F6D965, + 0x48F6D145, 0x00034AD3, 0x00080200, 0x00001000, @@ -547,19 +547,19 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00104120, 0x00000200, 0xAC0D5F80, - 0x7FFFFFFF, - 0x14F16080, - 0x1A041404, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, 0x00D00000, - 0x04864000, - 0x69A47A01, - 0xF228A3D5, - 0xF4D1451E, - 0x03529248, + 0x14864000, + 0x59647A05, + 0x8A28A3DD, + 0xF6D1451E, + 0x034AD348, 0x821A0000, 0x0000D000, 0x00000680, - 0xD559647A, + 0xDD59647A, 0x1E8A28A3, 0x48F6D145, 0x00034AD3, diff --git a/board/softing/vining_fpga/qts/pinmux_config.h b/board/softing/vining_fpga/qts/pinmux_config.h index 40b89123ec..f73ccbbabe 100644 --- a/board/softing/vining_fpga/qts/pinmux_config.h +++ b/board/softing/vining_fpga/qts/pinmux_config.h @@ -198,12 +198,12 @@ const u8 sys_mgr_init_table[] = { 0, /* NANDUSEFPGA */ 0, /* UART0USEFPGA */ 0, /* RGMII1USEFPGA */ - 1, /* SPIS0USEFPGA */ + 0, /* SPIS0USEFPGA */ 0, /* CAN0USEFPGA */ 0, /* I2C0USEFPGA */ 0, /* SDMMCUSEFPGA */ 0, /* QSPIUSEFPGA */ - 1, /* SPIS1USEFPGA */ + 0, /* SPIS1USEFPGA */ 1, /* RGMII0USEFPGA */ 0, /* UART1USEFPGA */ 0, /* CAN1USEFPGA */ @@ -211,7 +211,7 @@ const u8 sys_mgr_init_table[] = { 0, /* I2C3USEFPGA */ 0, /* I2C2USEFPGA */ 0, /* I2C1USEFPGA */ - 0, /* SPIM1USEFPGA */ + 1, /* SPIM1USEFPGA */ 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ }; diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h index 5d2a08ba00..fa04618336 100644 --- a/board/softing/vining_fpga/qts/pll_config.h +++ b/board/softing/vining_fpga/qts/pll_config.h @@ -13,7 +13,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -53,7 +53,7 @@ #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 #define CONFIG_HPS_CLK_OSC1_HZ 25000000 @@ -63,18 +63,12 @@ #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 488281 #define CONFIG_HPS_CLK_SDMMC_HZ 1953125 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_QSPI_HZ 320000000 #define CONFIG_HPS_CLK_SPIM_HZ 200000000 #define CONFIG_HPS_CLK_CAN0_HZ 12500000 #define CONFIG_HPS_CLK_CAN1_HZ 12500000 diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h index de9f0e4153..ec067eb473 100644 --- a/board/softing/vining_fpga/qts/sdram_config.h +++ b/board/softing/vining_fpga/qts/sdram_config.h @@ -47,7 +47,7 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 @@ -62,15 +62,15 @@ #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 @@ -149,7 +149,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b4 #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32 -- cgit v1.2.3 From 110861992f1ed1c21e0abd60f71e7f59c2462a0b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:34 +0200 Subject: ARM: socfpga: vining_fpga: Update environment Update board environment to match the one used in deployment. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- configs/socfpga_vining_fpga_defconfig | 2 +- include/configs/socfpga_vining_fpga.h | 106 ++++++++++++++++++++++++++-------- 2 files changed, 83 insertions(+), 25 deletions(-) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index faa4a17de5..a9c594e219 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -9,7 +9,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; else setenv bootdelay 5 ; setenv boottype norm ; fi" +CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; elif test -n \"$force_boottype\" ; then setenv bootdelay 1 ; setenv boottype \"$force_boottype\" ; setenv force_boottype ; saveenv ; else setenv bootdelay 5 ; setenv boottype norm ; fi" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index ef3221e1c8..debf3ea94b 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -11,8 +11,9 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ /* Booting Linux */ -#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb" +#define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run selboot" +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -30,8 +31,11 @@ * B: GPIO 78 ... the button between USB A ports * * The logic: - * if button B is not pressed, boot normal Linux system immediatelly - * if button B is pressed, wait $bootdelay and boot recovery system + * if button B is pressed, boot recovery system after 10 seconds + * if force_boottype is set, boot system depending on the value in the + * $force_boottype variable after 1 second + * if button B is not pressed and force_boottype is not set, boot normal + * Linux system after 5 seconds */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -41,21 +45,36 @@ "bootscript=boot.scr\0" \ "ubimtdnr=5\0" \ "ubimtd=rootfs\0" \ - "ubipart=ubi0:rootfs\0" \ + "ubipart=ubi0:vining-fpga-rootfs\0" \ "ubisfcs=1\0" /* Default is flash at CS#1 */ \ "netdev=eth0\0" \ - "hostname=vining_fpga\0" \ + "hostname=vining_fpga\0" \ "kernel_addr_r=0x10000000\0" \ - "mtdparts_0=ff705000.spi.0:" \ + "fdt_addr_r=0x20000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0" \ + "mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */ \ "1m(u-boot)," \ "64k(env1)," \ "64k(env2)," \ "256k(softing1)," \ "256k(softing2)," \ "-(rcvrfs)\0" /* Recovery */ \ - "mtdparts_1=ff705000.spi.1:" \ - "32m(rootfs)," \ + "mtdparts_0_256m=ff705000.spi.0:" /* 256MiB(+256MiB) config */ \ + "1m(u-boot)," \ + "64k(env1)," \ + "64k(env2)," \ + "256k(softing1)," \ + "256k(softing2)," \ + "14720k(rcvrfs)," /* Recovery */ \ + "64m(rootfs)," /* Root */ \ + "-(userfs)\0" /* User */ \ + "mtdparts_1_128m=ff705000.spi.1:" /* 16MiB+128MiB SF config */ \ + "64m(rootfs)," \ "-(userfs)\0" \ + "mtdparts_1_256m=ff705000.spi.1:" /* 256MiB+256MiB SF config */ \ + "-(userfs2)\0" \ "update_filename=u-boot-with-spl-dtb.sfp\0" \ "update_qspi_offset=0x0\0" \ "update_qspi=" /* Update the QSPI firmware */ \ @@ -64,6 +83,23 @@ "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ "fi ; " \ "fi\0" \ + "sf_identify=" \ + "setenv sf_size_0 ; setenv sf_size_1 ; " \ + "sf probe 0:0 && setenv sf_size_0 ${sf_size} ; " \ + "sf probe 0:1 && setenv sf_size_1 ${sf_size} ; " \ + "if test -z \"${sf_size_1}\" ; then " \ + /* 1x256MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ + "setenv mtdparts_1 ; " \ + "elif test \"${sf_size_0}\" = \"1000000\" ; then " \ + /* 16MiB+128MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_16m} ; " \ + "setenv mtdparts_1 ${mtdparts_1_128m} ; " \ + "else " \ + /* 256MiB+256MiB SF */ \ + "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ + "setenv mtdparts_1 ${mtdparts_1_256m} ; " \ + "fi\0" \ "fpga_filename=output_file.rbf\0" \ "load_fpga=" /* Load FPGA bitstream */ \ "if tftp ${fpga_filename} ; then " \ @@ -80,7 +116,11 @@ "addmisc=" \ "setenv bootargs ${bootargs} ${miscargs}\0" \ "addmtd=" \ - "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \ + "if test -z \"${sf_size_1}\" ; then " \ + "setenv mtdparts \"${mtdparts_0}\" ; " \ + "else " \ + "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \ + "fi ; " \ "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ "addargs=run addcons addmtd addmisc\0" \ "ubiload=" \ @@ -102,29 +142,47 @@ "setenv ubimtdnr 5 ; " \ "setenv mtdparts mtdparts=${mtdparts_0} ; " \ "setenv mtdids nor0=ff705000.spi.0 ; " \ - "setenv ubipart ubi0:rootfs ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ "else " \ - "setenv ubisfcs 1 ; " \ - "setenv ubimtd rootfs ; " \ - "setenv ubimtdnr 6 ; " \ - "setenv mtdparts mtdparts=${mtdparts_1} ; " \ - "setenv mtdids nor0=ff705000.spi.1 ; " \ - "setenv ubipart ubi0:rootfs ; " \ + "if test \"${sf_size_0}\" = \"1000000\" ; then "\ + /* 16MiB+128MiB SF */ \ + "setenv ubisfcs 1 ; " \ + "setenv ubimtd rootfs ; " \ + "setenv ubimtdnr 6 ; " \ + "setenv mtdparts mtdparts=${mtdparts_1} ; " \ + "setenv mtdids nor0=ff705000.spi.1 ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ + "else " \ + /* 256MiB(+256MiB) SF */ \ + "setenv ubisfcs 0 ; " \ + "setenv ubimtd rootfs ; " \ + "setenv ubimtdnr 6 ; " \ + "setenv mtdparts mtdparts=${mtdparts_0} ; " \ + "setenv mtdids nor0=ff705000.spi.0 ; " \ + "setenv ubipart ubi0:vining-fpga-rootfs ; " \ + "fi ; " \ "fi ; " \ "sf probe 0:${ubisfcs}\0" \ + "boot_kernel=" \ + "if test -z \"${sf_size_1}\" ; then " /* 1x256MiB SF */ \ + "imxtract ${kernel_addr_r} fdt@1 ${fdt_addr_r} && " \ + "fdt addr ${fdt_addr_r} && " \ + "fdt resize && " \ + "fdt set /soc/spi@ff705000/n25q00@1 status disabled && " \ + "bootm ${kernel_addr_r}:kernel@1 - ${fdt_addr_r} ; " \ + "else " \ + "bootm ${kernel_addr_r} ; " \ + "fi\0" \ "ubi_ubi=" \ - "run ubi_sfsel ubiload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run ubi_sfsel ubiload ubiargs addargs boot_kernel\0" \ "ubi_nfs=" \ - "run ubiload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run ubiload nfsargs addip addargs boot_kernel\0" \ "net_ubi=" \ - "run netload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run netload ubiargs addargs boot_kernel\0" \ "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run netload nfsargs addip addargs boot_kernel\0" \ "selboot=" /* Select from where to boot. */ \ + "run sf_identify ; " \ "if test \"${bootmode}\" = \"qspi\" ; then " \ "led all off ; " \ "if test \"${boottype}\" = \"rcvr\" ; then " \ -- cgit v1.2.3 From e6281b8ab07e0d64be3f5f829d5a3d3a08390daa Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jun 2019 00:19:35 +0200 Subject: ARM: socfpga: vining_fpga: Extract eth1 MAC from EEPROM The EEPROM contains eth1 MAC address as well, use it. Signed-off-by: Marek Vasut Cc: Silvio Fricke Cc: Simon Goldschmidt --- board/softing/vining_fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index 1e095a4e7d..3f597fb99e 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -87,6 +87,8 @@ int misc_init_r(void) /* Set ethernet address from EEPROM. */ if (!env_get("ethaddr") && is_valid_ethaddr(&data[0x62])) eth_env_set_enetaddr("ethaddr", &data[0x62]); + if (!env_get("eth1addr") && is_valid_ethaddr(&data[0x6a])) + eth_env_set_enetaddr("eth1addr", &data[0x6a]); return 0; } -- cgit v1.2.3