From 3e11ae80fec1ee12194940955431186abf6009c2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 17 Oct 2007 15:40:19 +0200 Subject: ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command Signed-off-by: Stefan Roese --- board/amcc/sequoia/cmd_sequoia.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index e7997e94db..6b9043a058 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -40,7 +40,7 @@ * All Sequoias & Rainiers select from two possible EEPROMs in Boot * Config F. One for 33MHz PCI, one for 66MHz PCI. The following * values are for the 33MHz PCI configuration. Byte 5 (0 base) is - * the only value affected for a 66MHz PCI and simply needs a +0x10. + * the only value affected for a 33MHz PCI and simply needs a | 0x08. */ #define NAND_COMPATIBLE 0x01 @@ -57,6 +57,7 @@ static char *config_labels[] = { "CPU: 416 PLB: 166 OPB: 83 EBC: 55", "CPU: 500 PLB: 166 OPB: 83 EBC: 55", "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + "CPU: 667 PLB: 133 OPB: 66 EBC: 66", "CPU: 667 PLB: 166 OPB: 83 EBC: 55", NULL }; @@ -97,6 +98,11 @@ static u8 boot_configs[][17] = { 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 }, + { + (NOR_COMPATIBLE), + 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, { (NAND_COMPATIBLE | NOR_COMPATIBLE), 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, -- cgit v1.2.3