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2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-14Revert "drivers/ddr/fsl: Dual-license DDR driver"Tom Rini
Upon further review, not all code authors are in favour of this change. This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-09drivers/ddr/fsl: Dual-license DDR driverYork Sun
To make this driver easier to be reused, dual-license DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Simon Glass <sjg@chromium.org> CC: Tom Rini <trini@konsulko.com> CC: Heinrich Schuchardt <xypron.glpk@gmx.de> CC: Thomas Schaefer <thomas.schaefer@kontron.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Robert P. J. Day <rpjday@crashcourse.ca> CC: Alexander Merkle <alexander.merkle@lauterbach.com> CC: Joakim Tjernlund <joakim.tjernlund@transmode.se> CC: Curt Brune <curt@cumulusnetworks.com> CC: Valentin Longchamp <valentin.longchamp@keymile.com> CC: Wolfgang Denk <wd@denx.de> CC: Anatolij Gustschin <agust@denx.de> CC: Ira W. Snyder <iws@ovro.caltech.edu> CC: Marek Vasut <marek.vasut@gmail.com> CC: Kyle Moffett <Kyle.D.Moffett@boeing.com> CC: Sebastien Carlier <sebastien.carlier@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Peter Tyser <ptyser@xes-inc.com> CC: Paul Gortmaker <paul.gortmaker@windriver.com> CC: Peter Tyser <ptyser@xes-inc.com> CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2016-09-26driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun
Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-14driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu
This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02armv8: ls1012a: Update Refresh cycle for DDRPrabhakar Kushwaha
Refresh cycle value must be selected based on the frequency of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT] should be based on round up (tREFI/tCK) formula. For 500MHz, mdref value should be 0x0f3c8000. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02armv8: ls1012a: Enable DDR row-bank-column decodingPrabhakar Kushwaha
Enable DDR row-bank-column decoding to decode DDR address as row-bank-column instead of bank-row-column for improving performance of serial data transfers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>