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path: root/include/fsl_immap.h
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2017-09-11fsl-layerscape: Consolidate registers space defination for CCI-400 busAshish Kumar
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14driver/ddr/fsl: Add more debug registersYork Sun
32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2015-05-20driver/ddr/fsl: Remove deskew_cntrl registerYork Sun
This register is reserved and shouldn't have been exposed. Accessing it may have unexpected result on different SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>