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Rather than relying on hard-coded offsets actually make use of
partition table parsing implementation.
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Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:5752
TEST=on Lumpy, test Ctrl+D behavior with and without usb-keyboard set
in the device tree.
Change-Id: I7bb2f6ea18f5edadea93f9e5d23ed49ed57a3b23
Reviewed-on: https://gerrit.chromium.org/gerrit/12589
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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BUG=chromium-os:23496
TEST=built Seaboard and Waluigi OK
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I9045f77032038435180b68c9a7f79c3f0cca1989
Reviewed-on: https://gerrit.chromium.org/gerrit/12391
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This reads the frequency of a named clock from the fdt.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: Ib35bf7ef749f51862644218b1015057ca4e25203
Reviewed-on: https://gerrit.chromium.org/gerrit/12243
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Move the malloc() out of fdt_decode_alloc_region() and rename it
accordingly. This makes the code somewhat cleaner and allows us
to print a sensible error message.
BUG=chromium-os:17062
TEST=build and boot on Kaen
Change-Id: I8edc8809baa42578e74c5e42cf47494b31b774e7
Reviewed-on: https://gerrit.chromium.org/gerrit/11878
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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BUG=chromium-os:21540
TEST=Built u-boot and booted u-boot on tegra2_kaen
Change-Id: Id6f11512ea1a95bd57b600601b488ae20b34db2d
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/10808
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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On the tegra30, it appears that the "DVC" i2c controller has been
normalized and no longer requires special semantics for accessing it
(it has also just been renamed to "i2c5"). This change makes it so
that we don't pick DVC semantics based on the periperal ID, but
instead allow the device tree to specify.
BUG=chromium-os:21540
TEST=Compiled / booted on Kaen
Change-Id: Idfd96d1193b5ac267c61416544c63cc03dab396d
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/10279
Reviewed-by: Simon Glass <sjg@chromium.org>
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Exclude kcrashmem from vboot unused memory wipe to allow for recovery of
kernel crash dumps. If the kcrashmem size changes, then the corresponding
fdt must be updated.
BUG=chrome-os-partner:5168
TEST=Manually observed kcrash preserved
Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org>
Change-Id: Iecb2bd7f7df958125ed3cb3bf0b789602e314e7c
Reviewed-on: http://gerrit.chromium.org/gerrit/8942
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Katie Roberts-Hoffman <katierh@chromium.org>
Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
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This line is a NC on Asymptote, but right now we're using the pwm line
(incorrectly). This CL removes the backlight-vdd line from Asymptote
dts and ensures that it's safely ignored if it's missing.
BUG=None
TEST=Built u-boot for Asymptote and flashed it on the device. Ensured that the
backlight still works in u-boot.
Change-Id: Id751b6756bac120e2211b7b32c58f356ff30b767
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/8063
Reviewed-by: Jon Kliegman <kliegs@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This function looks up a property in a node which contains a memory region
address and size. It returns a pointer to this address, but if the address
is zero, it is allocated with malloc() instead.
It is used to allocate Chrome OS GBB memory regions and the like.
BUG=chromium-os:19353
TEST=build for Seaboard
Change-Id: I91fe8656f3ea50839998ab0e16b023635adbc119
Reviewed-on: http://gerrit.chromium.org/gerrit/7640
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Simon Glass <sjg@chromium.org>
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This provides a way of reading a memory region size, analogous to addr_to_cpu.
BUG=chromium-os:17062
TEST=build for Seaboard
Change-Id: I7392c8d72fb65fb978b44068cf7ccb0ad2d4aeec
Reviewed-on: http://gerrit.chromium.org/gerrit/7643
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Simon Glass <sjg@chromium.org>
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This corrects a compile erron when DEBUG is defined in fdt_decode.
Also change property to prop_name throughout, for consistency.
BUG=chromium-os:19353
TEST=build for Seaboard
Change-Id: I7503343cea20b556afeb0e507ce9d2cf2165c837
Reviewed-on: http://gerrit.chromium.org/gerrit/7639
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Simon Glass <sjg@chromium.org>
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This fixes what would become a build break if a board did not have NS16550
serial support included. T30 needs this change.
Change-Id: I6e06dd7f7fce7e475c0cbe48edae8d068ca5b7e8
Reviewed-on: http://gerrit.chromium.org/gerrit/7637
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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BUG=chromium-os:17062
TEST=build and boot on Seaboard
Change-Id: I7aa667fc608d3c42b4e16b0b9af3ef34df425cd0
Reviewed-on: http://gerrit.chromium.org/gerrit/6070
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/7453
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cros_gpio module used a ad-hoc format of GPIO config, and it should
use <&gpio ...> instead. This patch changes the format of GPIO config.
Note: In between calls to gpio_direction_input() (in fdt_setup_gpio())
and calls to gpio_get_value(), you have to insert a small delay if the
input source is connected to the GPIO through a sufficiently large
series resister (say, 200K ohm) so that the RC time constant for
charging the gate capacitance on the input is non-trivial.
As a matter of fact, I tested on Kaen and Aebl, and found only write
protect GPIO needs this delay, and the delay time is less than 10 us.
And we may safely hide this delay by decoupling the initialization and
reading of GPIOs.
BUG=none
TEST=Run "vboot_test gpio" on Kaen and Aebl, and check GPIO readings
TEST=Run "crossystem" on Kaen and Aebl after boot, and check GPIO readings
Change-Id: Ib4d93c2ce156eb09ffc24a3882f83490d25c1e91
Reviewed-on: http://gerrit.chromium.org/gerrit/5726
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
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This is needed to use the same config files for all x86 platforms,
while the right incarnation of register accesses is determined by
the device tree.
BUG=chrome-os-partner:4520
TEST=boot u-boot on Alex and Stumpy, get serial output on both.
Change-Id: Ibb8192657861713d656358c5f085f6dde2cb1365
Reviewed-on: http://gerrit.chromium.org/gerrit/6248
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
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fdt_decode module is able to decode GPIO configurations (GPIO number,
I/O direction, and polarity). But the GPIO decoder was kept private to
fdt_decode module because GPIOs were generally used to control a larger
device (LCD, for example) and so considering a single GPIO in isolation
usually did not make much sense.
However, we are aware that there are cases that a GPIO is not a part of
any other larger device, but a standalone prober of hardware status. In
these cases, decoding a single GPIO does make sense. Thus, we expose the
GPIO decoder to public interface.
As this patch only changes functions from static to non-static and
function names, I only tested it builds or not.
BUG=none
TEST=build for Aebl successfully
Change-Id: Ic5f19b64f0cf3f64c56adead7c57e480ef24cab8
Reviewed-on: http://gerrit.chromium.org/gerrit/5725
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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LCD panels require delays in the power-on sequence. This adds those with
a facility for the ftd to specify them.
This introduces significant boot delays - around 120ms at minimum. We will
address these with further work.
BUG=chrome-os-partner:4854
TEST=Probe these power signals on Aebl with a scope.
Boot on Seaboard
Change-Id: Ie12abd52b66db5966de985a102aaadaea7f3d970
Signed-off-by: Dilan Lee <dilee@nvidia.com>
Reviewed-on: http://gerrit.chromium.org/gerrit/4194
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
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BUG=chromium-os:17950
TEST=build without error, pending test until we use it to clear the ram regions.
Change-Id: Icf7695e7ca512541dc77cd84397818e6392f2e9a
Reviewed-on: http://gerrit.chromium.org/gerrit/4479
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
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BUG=chromium-os:17064
TEST=Build U-Boot
Run "i2c probe" for each i2c bus on Seaboard, Kaen and Aebl
Change-Id: I1528a6c08d500c001a1210f9947c494b7ffc81f6
Reviewed-on: http://gerrit.chromium.org/gerrit/4049
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The raw gpio readings are not the logical values of true/false. A gpio
may connect to device that is either high active or low active. That is,
a raw reading of 1 from low active device actually means "false". In
this context, we refer to this as a gpio's polarity. Note that a gpio
polarity may differ board by board, depending on the actual wiring of
the board.
The u-boot and the crossystem (a user space program) needs the
polarities to correctly interpret the raw gpio readings. The crossystem
needs polarities for the gpio values in the crossystem data blob that
u-boot passes to kernel (these values are "post-interpretation").
Instead, the crossystem is required to read "current" raw gpio readings
and interpret these readings to a user.
Note: I merely copied polarity configuration to kaen and aebl, but I did
not test its correctness.
BUG=chromium-os:16508
TEST=boot on Seaboard
1. Turn on Seaboard with dev switch on and rec switch off
2. Check debug output of u-boot
----------------------------------------
cros_onestop_firmware: polarity:
cros_onestop_firmware: - wpsw: 1
cros_onestop_firmware: - recsw: 0
cros_onestop_firmware: - devsw: 1
cros_onestop_firmware: gpio value:
cros_onestop_firmware: - wpsw: 1
cros_onestop_firmware: - recsw: 0
cros_onestop_firmware: - devsw: 1
----------------------------------------
2. Check /proc/device-tree/crossystem/
----------------------------------------
$ od -x polarity_write_protect_sw
0000000 0000 0100
0000004
$ od -x polarity_recovery_sw
0000000 0000 0000
0000004
$ od -x polarity_developer_sw
0000000 0000 0100
0000004
----------------------------------------
Change-Id: Ie92c31ce0abddf0271e73669b429621deaed76dd
Reviewed-on: http://gerrit.chromium.org/gerrit/3650
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
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BUG=chromium-os:11623
TEST=build on Seaboard, Kaen, Aebl, see that machine type is correct
Change-Id: Icc9ab0172e459cbd0f5ac05041dac2f4327a2de6
Reviewed-on: http://gerrit.chromium.org/gerrit/3595
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Move this code into fdt_decode so avoid changing board.c too much.
The new implementation just looks at the 'model' property in the root of the
tree so does not require a lookup.
BUG=chromium-os:11623
TEST=build and boot, see that we still have board information displayed
Change-Id: I68dd420cfa6a2af6e9885bc457e46056c85f74a0
Reviewed-on: http://gerrit.chromium.org/gerrit/3500
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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As expected write-through caching slows the LCD frame buffer to an
unacceptable degree. This change provides an option to use write-back, with
a dcache flush after each puts(), clear screen or scroll. This option
becomes the default unless overwritten in the fdt.
Timings (done with about 2 screenfuls of vboot debug output):
flushing dcache after each line
write-through cache:
Timer summary in microseconds:
Mark Elapsed Stage
0 0 awake
2,418,290 2,418,290 bootm_start
no cache logic (tearing!):
Timer summary in microseconds:
Mark Elapsed Stage
0 0 awake
1,434,217 1,434,217 bootm_start
This commit:
Timer summary in microseconds:
Mark Elapsed Stage
0 0 awake
1,500,866 1,500,866 bootm_start
BUG=chromium-os:17047
TEST=build and boot on Seaboard, check for LCD tearing.
Change-Id: I2155f9c4ad3b59376f1b713daed77cf5aac396a4
Reviewed-on: http://gerrit.chromium.org/gerrit/3313
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This adds support for the Ctrl modifier. The left and right ctrl keys are
dealt with in the same way.
BUG=chromium-os:11623
TEST=boot U-Boot modified to print hex codes of input characters. Run through
ctrl-A to ctrl-Z and see that correct output results
Change-Id: Ibcaa2f401fce7f2ace457d4068a823caf74a8e9b
Reviewed-on: http://gerrit.chromium.org/gerrit/3354
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This adds a function for reading key tables from the fdt.
BUG=chromium-os:17034
TEST=boot U-Boot; type plain, shift and fn keys and check that the correct
output results
Change-Id: Ifb24f8bf143689ecb0f65c034a7d1b85a4d523ba
Reviewed-on: http://gerrit.chromium.org/gerrit/3333
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The general mmc register call (mmc_register) always sets MMC media as
removable. We define the removable flag explicitly and set the internal
eMMC media as non-removable.
A new fdt field removable is also defined.
BUG=chromium-os:16543
TEST=Only able to test compilation withour error. Detailed test should see:
http://gerrit.chromium.org/gerrit/#change,2835
Change-Id: Ib8b1742f74c5a9e3fde3801e18c168d00fce47db
Reviewed-on: http://gerrit.chromium.org/gerrit/2894
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
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Load boot command from /config/bootcmd of device tree if none of the
environment variables that set boot command exist. These variables
may include failbootcmd, altbootcmd, and bootcmd.
BUG=chromium-os:16508
TEST=manual
1. Make sure you do not define any CONFIG_BOOTCOMMAND or equivalent
2. Add "bootcmd" property to your /config node of dts:
config {
...
bootcmd = "echo '**** load boot command from fdt! ****'";
};
3. Run u-boot and see that message prints out
Change-Id: I0ca6a777e23c1a8f024fada24ed507dc2e6fd898
Reviewed-on: http://gerrit.chromium.org/gerrit/3150
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
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This adds FDT configuration of USB ports.
BUG=chromium-os:11623
TEST=Build and boot u-boot; run mmc_boot
Change-Id: I62c015c64e3c3d9996b7117136eb636333fdc0e1
Reviewed-on: http://gerrit.chromium.org/gerrit/2781
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This adds support for a single GPIO as well as a list.
The GPIO flags cell is now used, where the bits are defined as:
Bit Meaning
=====================
0 GPIO is an output (1=output, 0=input)
1 Value to set if an output (1=high, 0=low)
BUG=chromium-os:11623
TEST=build and boot on Seaboard
Change-Id: I7084f3cbac9c33fe592ebf39332593b9a4631425
Reviewed-on: http://gerrit.chromium.org/gerrit/2779
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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USB port numbering was previously ad-hoc according to the position of the
ports in the FDT file. This change defines aliases to control this
explicitly: usb0, usb1, ...
BUG=chromium-os:11623
TEST=usb start; run usb_boot
Change-Id: Ifed6e1e9e21750bd0edf5d2bddc4afd3468ad7f4
Reviewed-on: http://gerrit.chromium.org/gerrit/2538
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
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This adds FDT configuration of USB ports.
BUG=chromium-os:11623
TEST=Build and boot u-boot; usb start; network boot
Change-Id: Ia3ea9f7ce816575dc0d99900a163d20e9cb65ecc
Reviewed-on: http://gerrit.chromium.org/gerrit/2348
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
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This was a structure but can simply be a string.
BUG=chromium-os:11623
TEST=build U-Boot
Change-Id: I89b32266739f394f416f0abbae529213788f863d
Reviewed-on: http://gerrit.chromium.org/gerrit/2347
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
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This adds functions to decode LCD information from the FDT.
BUG=chromium-os:11623
TEST=build and boot U-Boot on Seaboard
Change-Id: Ia0183f19c24b293fa845d8e137b49922cbd59005
Reviewed-on: http://gerrit.chromium.org/gerrit/1762
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
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BUG=chromium-os:13228
TEST=Build, boot on Seaboard
Change-Id: Ifd1db8b0acdbe63c68372418f35c3e76882dc6e0
Reviewed-on: http://gerrit.chromium.org/gerrit/1288
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This adds a new console serial port which is implemented by the driver
selected in the device tree.
BUG=chromium-os:11623
TEST=build and boot U-Boot on Seaboard
Change-Id: I0e41f795a78d165c2907a9f8faeeabe1a2639a18
Reviewed-on: http://gerrit.chromium.org/gerrit/958
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Rather than having the Seaboard SPI/UART switch in CONFIG options in the
header files, use the device tree to configure this
BUG=chromium-os:11623
TEST=build and boot U-Boot on Seaboard
Change-Id: If3b92b685b5fe31a97ef4bc3578a6aa00208d827
Reviewed-on: http://gerrit.chromium.org/gerrit/1661
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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To select between different drivers we need to translate the compatible
string into an ID number which we can use to select between different
drivers for each function.
BUG=chromium-os:11623
TEST=build and boot U-Boot on Seaboard
Change-Id: I99a60f7e92a021cb7e23a85054e6b76cb9f2054c
Reviewed-on: http://gerrit.chromium.org/gerrit/957
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
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The fdt_decode library will help drivers access the FDT. This first
starting point implements functions to access information about the console
UART.
BUG=chromium-os:11623
TEST=build and boot U-Boot on Seaboard
Change-Id: I7ff7e5c1d9c38a6301d02d38fb4b993306ca18bd
Reviewed-on: http://gerrit.chromium.org/gerrit/954
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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