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- P2020 Rev 2.0 eSDHC PIO support no longer needed.
- P2020 Rev 2.0 has same issue of eSDHC can't operate at 1.8v
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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On Rev 1.0 of P1022 and P1020 eSDHC controller can't work at 1.8v.
To remove the capability of the controller, this work around has
added to unset the 1.8v field in Host capabilities register.
Signed-off-by: Huang Changming <R66093@freescale.com>
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Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
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Modified the default othbootargs to include the cache-sram-size
parameter.This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.
And also modified nandboot uImage and dts partition offsets.
Signed-off-by: Rajesh Gumasta <Rajesh.Gumasta@freescale.com>
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To use,
tftp 11000000 u-boot.bin,
go 1107f000
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Enable environment support for eSDHC/eSPI boot on P1 and P2 RDB platforms.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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1. Modified the tsec_mdio structure to include the new regs
2. Modified the MDIO_BASE_ADDR so that it will handle both
older version and new version of etsec.
Signed-off-by: Sandeep Kumar <Sandeep.Kumar@freescale.com>
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This patch enables the eSPI configuration to use
the Spansion Flash on P1 and P2 RDB Platforms
This also enables the Intel Pro/1000 PT Gb Ethernet
PCI-E Network Adapter configuration support
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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DDR support to boot from NAND/eSDHC/eSPI on P1 & P2 RDB platforms.
Specifically, this support is needed when
L2 Cache size is less than 512K.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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On P1 and P2 RDB Platforms, read the I2C EEPROM to
get various board switch settings like NOR Flash
Bank selection, SD Data width etc.
Depending on,
switch SW5[6] - select width for eSDHC
ON - 4-bit [Enable eSPI]
OFF - 8-bit [Disable eSPI]
switch SW4[8] - NOR Flash Bank selection for Booting
OFF - Primary Bank
ON - Secondary Bank
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
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Neither the MVBLUE nor its underlying architecture implement the
do_irqinfo() function which is required when CONFIG_CMD_IRQ is defined.
This change fixes the following MVBLUE compiler error:
-> ./MAKEALL MVBLUE
Configuring for MVBLUE board...
common/libcommon.a(cmd_irq.o):(.u_boot_cmd+0x24): undefined reference to `do_irqinfo'
make: *** [u-boot] Error 1
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
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The support for this was silently dropped by a configuration
split during the merge of the imx27lite board support in commit
864aa034f3a0e10ce710e8bbda171df3cab59414 (cmd_mtdparts: Move to common
handling of FLASH devices via MTD layer).
Signed-off-by: Detlev Zundel <dzu@denx.de>
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A typo caused the stack and malloc regions to overlap, which prevented
mem_malloc_init() from returning. This commit makes the memory layout match
the example described in include/configs/microblaze-generic.h
Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
Signed-off-by: Michal Simek <monstr@monstr.eu>
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A bunch of the 85xx boards have this cruft in them - it's not used
anywhere. Delete it.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
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This patch adds a default bootargs "fbmem" value to the
CONFIG_BOOTARGS string for the MIMC200 board.
Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
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This patch fixes an ugly behavior of the IL712 magnetic couplers
as used on PLU405. These parts will remember their last state
over a power cycle which might cause unwanted behavior.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
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Both lpd7a400 and lpd7a404 failed to compile because they had
CONFIG_SMC_USE_IOFUNCS defined:
examples/standalone/smc91111_eeprom.c:388: undefined reference to `SMC_outw'
Also removed an orphaned paren in lpd7a404.h
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This patch fixes a problem only seen very occasionally on Canyonlands.
The NOR flash interface (CFI driver) doesn't work reliably in all cases.
Erasing and/or programming sometimes doesn't work. Sometimes with
an error message, like "flash not erased" when trying to program an
area that should have just been erased. And sometimes without any error
messages. As mentioned above, this problem was only seen rarely and with
some PLL configuration (CPU speed, EBC speed).
Now I spotted this problem a few times, when running my Canyonlands with
the following setup (chip_config):
1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100
Changing the EBC configuration to not release the bus into high
impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1
in EBC0_CFG) seems to fix this problem. I haven't seen any failure
anymore with this patch applied.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: David Mitchell <dmitchell@amcc.com>
Cc: Jeff Mann <MannJ@embeddedplanet.com>
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The comment for the BR0_PRELIM port size initialization incorrectly
stated 32 bit, while it's actually 16 bit. The code is correct.
Reported-by: Guenter Koellner <guenter.koellner@nsn.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
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The patch fixes a compilation warning by defining
CONFIG_SYS_64BIT_VSPRINTF in the config file
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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The patch fixes a compilation warning by defining
CONFIG_SYS_64BIT_VSPRINTF in the config file
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use
reset to retry. Define default bootcommand and bootargs for production.
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Simply add some defines, and adjust TLBe setup to include some
space for eLBC NAND.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.
Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).
So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Start of support of
Texas Instruments Software Development Platform(SDP)
for OMAP3430 - SDP3430
Highlights of this platform are:
Flash Memory devices:
Sibley NOR, Micron 8bit NAND and OneNAND
Connectivity:
3 UARTs and expanded 4 UART ports + IrDA
Ethernet, USB
Other peripherals:
TWL5030 PMIC+Audio+Keypad
VGA display
Expansion ports:
Memory devices plugin boards (PISMO)
Connectivity board for GPS,WLAN etc.
Completely configurable boot sequence and device mapping
etc.
Support default jumpering and:
- UART1/ttyS0 console(legacy sdp3430 u-boot)
- UART3/ttyS2 console (matching other boards,
and SDP HW docs)
- Ethernet
- mmc0
- NOR boot
Currently the UART1 is enabled by default. for
compatibility with other OMAP3 u-boot platforms,
enable the #define of CONSOLE_J9.
Conflicts:
Makefile
Fixed the conflict with smdkc100_config by moving omap_sdp3430_config
to it is alphabetically sorted location above zoom1.
Signed-off-by: David Brownell <david-b@pacbell.net>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
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Forgot to add Copyright while submitting the patch.
This patch adds the copyright.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch removes the Sequoia "bootstrap" command and replaces it
with the now common command "chip_config".
Please note that the patches with the dynamic PCI sync clock
configuration have to be applied, before this one should go in.
This is because Sequoia has 2 different bootstrap EEPROMs, and
the old bootstrap command configured different values depending
on the detected PCI async clock (33 vs. 66MHz). With the PCI sync
clock patches, this is not necessary anymore. The PCI sync clock
will be configured correctly on-the-fly now.
Signed-off-by: Stefan Roese <sr@denx.de>
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Till now only the ranges in the ebc node are updated with the values
currently configured in the PPC4xx EBC controller. With this patch now
the NOR flash size is updated in the device tree blob as well. This is
done by scanning the compatible nodes "cfi-flash" and "jedec-flash"
for the correct chip select number.
This size fixup is enabled for all AMCC eval board right now. Other
4xx boards may want to enable it as well, if this problem with multiple
NOR FLASH sizes exists.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
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Fix compile error:
include/configs/mcc200.h:401:6: error: #elif with no expression
Signed-off-by: Wolfgang Denk <wd@denx.de>
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Adding the CONFIG_SYS_64BIT_VSPRINTF fot the DM644x based Sonata
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adding the CONFIG_SYS_64BIT_VSPRINTF in the DVEVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM365 EVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adding the CONFIG_SYS_64BIT_VSPRINTF in the DM355 EVM config.
Without this option enabled while performing NAND operations we will get
wrong diagnostic messages.
Example if the MTD NAND driver find a bad block while erasing from
a certain address, it will say bad block skipped at 0x00000000.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch removes dependency on the sizes.h header file
and removes all references to SZ_xx.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Update default environment to support new kernel DSS2 subsystem and
simplify rootfs type and location changes.
Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
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This patch adds support for the leopard board which is
based on the DM355 SOC.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds the initial support for DM6467 EVM.
Other features like NET and NAND support will be added as follow up patches.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This change fixes the compiler warning
main.c: In function 'abortboot':
main.c:122: warning: too few arguments for format
Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
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This change fixes the compiler warning
nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF
for correct output!
Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
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Correct the chip select configuration for the nand flash chip select.
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
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This is an orphaned legacy leftover that is just polluting
the config file namespace.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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On Chip BootROM support for P1 and P2 series RDB platforms.
This patch is derived from latest On Chip BootROM support on MPC8536DS
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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NAND Boot support for P1 and P2 series RDB platforms.
This patch is derived from NAND Boot support on MPC8536DS.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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