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path: root/include/configs/xilinx_versal.h
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2019-06-14net: Convert CONFIG_TFTP_BLOCKSIZE to KconfigMarek Vasut
Convert CONFIG_TFTP_BLOCKSIZE to Kconfig, update defconfigs, headers and whitelist. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2019-06-14net: Convert CONFIG_IP_DEFRAG to KconfigMarek Vasut
Convert CONFIG_IP_DEFRAG to Kconfig, update defconfigs, headers and whitelist. This patch is a follow-up on a patch by Christian Gmeiner with the added config/header/whitelist updates. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2019-02-14arm64: versal: Define distro boot commnads for qspi ospi and mmcSiva Durga Prasad Paladugu
This patch adds distro boot commands for qspi, ospi and mmc. The distro boot commands now reads the script from flash offset of 63.5MB for qspi and ospi and executes it. For mmc its same as generic distro boot command. As either one of the qspi or ospi can exist on hardware, defined a single distroboot command as xspi that works for both. Setup default location via script_offset_f to 63.5MB to match the most xilinx reference boards for qspi, ospi for now. 512kB allocated space for script size (script_size_f) should be more than enough to cover custom boot logic. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>