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Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
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This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.
Signed-off-by: Stefan Roese <sr@denx.de>
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Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
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- Introduced dedicated switches for building 440 and 405 images required
for 440-specific machine instructions like 'rfmci' etc.
- Exception vectors moved to the proper location (_start moved away from
the critical exception handler space, which it occupied)
- CriticalInput now serviced (with default handler)
- MachineCheck properly serviced (added a dedicated handler and return
subroutine)
- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
unhandled and those not relevant for 4xx were eliminated)
- Eliminated Linux leftovers, removed dead code
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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A '3' got cut off in the formatting of the last patch to automatically
change the clock speed of the system clock on sequoia board.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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The AMCC Secquoia board has been changed in a new revision from using a
33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD
indicates the difference. This patch reads that bit and uses the correct
clock speed for the board. This code is backward compatable will all
prior boards. All prior boards will be read as 33.000.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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As spotted by Matthias Fuchs, the READY input should not be
enabled for the NOR FLASH on the Sequoia board.
Signed-off-by: Stefan Roese <sr@denx.de>
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When PCI PNP is enabled the pci pnp configuration routine is called
which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some
problems with some PCI cards. For now disable the PCI PNP configuration.
Signed-off-by: Stefan Roese <sr@denx.de>
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The config file now handles the 2nd target, the Rainier (440GRx)
evaluation board better. Additionally the PPC input clock was
adjusted to match the correct value of 33.0 MHz.
Signed-off-by: Stefan Roese <sr@denx.de>
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This code will optimize the DDR2 controller setup on a board specific
basis.
Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: Stefan Roese <sr@denx.de>
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The current NAND Bootloader setup forces the environment
variables to be in line with the bootloader. This change
enables the configuration to be made in the board include
file instead so that it can be individually enabled.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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Based on idea and implementation from Jeff Mann
Patch by Stefan Roese, 20 Oct 2006
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Patch by Stefan Roese, 13 Sep 2006
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Patch by Stefan Roese, 12 Sep 2006
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- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
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