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path: root/include/configs/T4240QDS.h
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2013-11-21mtd: move & update nand_ecclayout structure (plus board changes)Prabhakar Kushwaha
nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Changes from Prabhabkar's version (squashed into one patch to preserve bisectability): - Added _LARGE to MTD_MAX_*_ENTRIES This makes the names match current Linux source, and resolves a conflict between http://patchwork.ozlabs.org/patch/280488/ and http://patchwork.ozlabs.org/patch/284513/ The former was posted first and is closer to matching Linux, but unlike Linux it does not add _LARGE to the names. The second adds _LARGE to one of the names, and depends on it in a subsequent patch (http://patchwork.ozlabs.org/patch/284512/). - Made max oobfree/eccpos configurable, and used this on tricorder, alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build for me without doing so, due to a size increase). On tricorder SPL, this saves 2576 bytes (and makes the SPL build again) versus the new default of 640 eccpos and 32 oobfree, and saves 336 bytes versus the old default of 128 eccpos and 8 oobfree. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Vipin Kumar <vipin.kumar@st.com> [scottwood@freescale.com: changes as described above] Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Thomas Weber <weber@corscience.de> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Cc: Stefan Roese <sr@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2013-10-31powerpc/esdhc: Add 3.3v voltage support in esdhc capacity registerHaijun.Zhang
T4240QDS eSDHC host capabilities reigster should have VS33 bit define. Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity missing Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2013-10-16powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.hPo Liu
This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-08-09powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian
1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09powerpc/mpc8xxx: Add memory reset controlYork Sun
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09powerpc/T4240EMU: Add T4240EMU targetYork Sun
Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: York Sun <yorksun@freescale.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-14powerpc/t4240qds: Move SoC define into boards.cfgYork Sun
Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC variants supported on the same board. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/t4qds: Add T4QDS boardYork Sun
The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>