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At HS400 mode the ITAPDLY value is that from High Speed mode
which is incorrect and may cause boot failures.
The ITAPDLY for HS400 speed mode should be the same as ITAPDLY
as HS200 timing after tuning is executed. Add the functionality
to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY.
Upstream-Status: Backport [f13a830e6e4ad884069e25c7cd2dc333b474da98]
Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez <jm@ti.com>
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According to the device datasheet [0], ENDLL=1 for
DDR52 mode, so call am654_sdhci_setup_dll() and write
itapdly after since we do not carry out tuning.
[0] https://www.ti.com/lit/ds/symlink/am62p.pdf
Upstream-Status: Backport [a124e31a97cd2963181d3a8a00678998bf9958a2]
Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Set itap_del_ena if ITAPDLY is found in DT or if the tuning
algorithm was executed and found the optimal ITAPDLY. Add the
functionality to save ITAPDLYENA that can be referenced later
by storing the bit in array itap_del_ena[].
Upstream-Status: Backport [056af04a39aef6d9777a8d4fc29917b4494db4a5]
Signed-off-by: Judith Mendez <jm@ti.com>
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U-Boot is failing to boot class U1 UHS SD cards due to incorrect
OTAP and ITAP delay select values. Update OTAP and ITAP delay select
values from DT.
Upstream-Status: Backport [5048b5c61afddddb0a6ff2e6bffdd9dd028e399b]
Fixes: c7d106b4eb3 ("mmc: am654_sdhci: Update output tap delay writes")
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
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Currently the sdhci_am654 driver only supports one tuning
algorithm which should be used only when DLL is enabled. The
ITAPDLY is selected from the largest passing window and the
buffer is viewed as a circular buffer.
The new tuning algorithm should be used when the delay chain
is enabled; the ITAPDLY is selected from the largest passing
window and the buffer is not viewed as a circular buffer.
This implementation is based off of the following paper: [1].
Also add support for multiple failing windows.
[1] https://www.ti.com/lit/an/spract9/spract9.pdf
Upstream-Status: Backport [6b8dd9ca6e06bc9ebd3d55cbbe094d4947e197bf]
Fixes: a759abf569d4 ("mmc: am654_sdhci: Add support for software tuning")
Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
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If SPL is passing video handoff structure to U-boot then it is safe to
assume that SPL has already enabled video and that's why it is passing
video handoff structure to U-boot so that U-boot can preserve the
framebuffer.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Fill video handoff fields in video_post_probe as at this point we have
full framebuffer-related information.
Also fill all the fields available in video hand-off struct as those
were missing earlier and U-boot framework expects them to be filled for
some of the functionalities.
While filling framebuffer size in video hand-off structure use the
actual framebuffer region size as derived from gd->video_top and
gd->video_bottom instead of directly using the size populated in
video_uc_plat as it contains unaligned size.
Reported-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address
bits minus 16 that are used to determine the mask used to detect
memory rollover and prevent aliasing and false coherency issues.
Set SDRAM_IDX using the device private data, ddr_ram_size for AM64x,
AM62x and AM62x SIP.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Acked-by: Bryan Brattlof <bb@ti.com>
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OSPI boot was broken due to wrong pairing of DMA
Fixes: 61ea32c0eb0c ("dma: ti: k3-udma: Use ring_idx to pair k3 nav rings")
Reported-by: Minas Hambardzumyan <minas@ti.com>
Cc: MD Danish Anwar <danishanwar@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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I do not think the R5 SPL will initialize non static variables (I didn't
find and evidence of it) so we want to ensure this is a constant.
Signed-off-by: Bryan Brattlof <bb@ti.com>
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The AM64x and some of the AM62xx family of devices use the same 16b
controller though only the AM64x is limited to 2GB addressable.
Annoyingly the address alias detection machinery defaults to the full
8GB for the AM64x. Reset this value to 2GB only if we're initializin DDR
on an am64x device
Signed-off-by: Bryan Brattlof <bb@ti.com>
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Add support for AM64x by adding it's compatible in pruss driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Add support for AM64x PRU cores by adding compatibles for AM64x.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node.
Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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ICSSG firmware supports FDB commands. Add support to send FDB commands
from driver. Once rx_flow_id is obtained from dma, let firmware know that
we are using this rx_flow_id by sending a FDB command.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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This is the PURSS Ethernet driver for TI AM654 Sr2.0 and laterSoCs with
the ICSSG PRU Sub-system running EMAC firmware. This driver caters to
either of the slices of the icssg subsystem.
One and exactly one of the slices is supported as the u-boot ethernet
supports probing one interface at a time.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Add icssg_queue.c file. This file introduces macros and APIs related to
ICSSG queues. These will be used by ICSSG Ethernet driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Add icssg_config.h / .c and icssg_classifier.c files. These are firmware
configuration and classification related files. Add MII helper APIs and
MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver.
Also introduce icssg_prueth.h which has definition of prueth related
structures.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Add firmware interface related headers and macros for ICSSG Ethernet
driver. These macros will be later used by the ICSSG ethernet driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Add APIs to set a firmware_name to a rproc and boot the rproc with the
same firmware.
Clients can call rproc_set_firmware() API to set firmware_name for a rproc
whereas rproc_boot() will load the firmware set by rproc_set_firmware() to
a buffer by calling request_firmware_into_buf(). rproc_boot() will then
load the firmware file to the remote processor and start the remote
processor.
Also include "fs-loader.h" and make remoteproc driver select FS_LOADER in
Kconfig so that we can call request_firmware_into_buf() from remoteproc
driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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The fs-loader driver reads env storage_interface and uses it to load
firmware file into memory using the medium set by env. Update the driver
to use env fw_storage_interface as this variable is only used to load
firmwares. This is to keep all variables used by fs-loader driver with
'fw_' prefix. All other variables have 'fw_' prefix except for
storage_interface.
The env storage_interface will act as fallback so that the
existing implementations do not break.
Also update the FS Loader documentation accordingly.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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Add driver for TPS6287x step down convertors
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
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Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
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Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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restricted to 32 bits' issue
As R5 is a 32 bit processor, the RAM banks' base and size calculation
is restricted to 32 bits, which results in wrong values if bank's base
is greater than 32 bits or bank's size is greater than or equal to 4GB.
So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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The 1-bit inline ECC support in TI's DDRSS bridge requires
the configured memory regions to be preloaded with a pattern
before use. This is done by the k3-ddrss driver from the
R5 SPL in a 'for' loop. It takes around 10 seconds to fill
2GB of memory, for example. Memset can cut the time in half
and using DMA currently yields a similar result.
The BIST engine of DDR controller provides support for
initializing any memory region with a pattern. This
bypasses the DDRSS bridge, so the required inline ECC
data is not computed and populated in the memory. For
some values like zero, the computed ECC syndrome is also
zero and we can use these values to preload the memory
from the DDR controller, without the assistance of the
bridge.
The registers involved in the process are described in the
'DDR controller registers' topic in [1] AM62 and [2] J721E
reference manuals.
The patch replaces the 'for' loop memory fill function with
the BIST memory initialization procedure. This cuts the time
to preload the 2GB memory from 10 seconds down to 1 second.
The bist preload function uses the lpddr4 APIs in the k3-ddrss,
so this is compatible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.
A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.
Fix the issue by disabling all IRQs at probe.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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pr_info() depends on CONFIG_LOGLEVEL > 6. If user has
enabled CONFIG_TI_GPMC_DEBUG then we should print the
GPMC settings/timings regardless of CONFIG_LOGLEVEL.
So use printf() instead of pr_info().
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Use device-tree node property names for parsing nodes instead of
indexing as indexing could be different between different SoCs based on
number of DSS entities available on that particular SoC.
Also correct the video layer naming in driver to match to actual one
being used in upstream DSS device-tree node [1].
This also fixes AM62x splash screen usage using the latest upstream DSS
device-tree nodes where hard-coded indexing which driver was using
before this patch was not matching the correct properties in the DT
node.
[1]: Upstream AM62x DSS node:
https://github.com/torvalds/linux/blob/v6.8-rc1/arch/arm64/boot/dts/ti/k3-am62-main.dtsi#L774
Fixes: 5f9f816bb8 ("drivers: video: tidss: TIDSS video driver support
for AM62x")
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
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Adds a check for K3_OPP_LOW config and will change MPU freq/voltage
and msmc clock according to opp_low spec.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Useful when trying to check if an opp efuse is burned in or not.
k3_avs driver checks opp_ids when probing and overwrites the voltage
values in vd_data for the respective board. This can be called to check
that data and returns 0 if valid.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Upstream u-boot changed to using the ti,j7200-vtm compatible with
the Linux 6.6 DT sync, so using the same here
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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Add opp_low to j721e vd_data
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
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PSIL mapping is same as AM62P other than extra instances of CSI-RX.
Reuse the same file and add CSI PSIL mapping there.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the static DMA channel data for using DMA at SPL stage
for J722S SoC family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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The J722S family of SoCs uses the same DDR controller as found on the
AM62A family. Enable this option when building for the J722S family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Introduce support for J722S SoC.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the part number for TI's j722s family of SoC
to identify it during boot.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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The macro ELM_BASE is defined in mach/hardware.h and is
not visible at the omap_elm.h header file. Avoid using it
in omap_elm.h.
Reported-by: Hong Guan <hguan@ti.com>
Fixes: 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model support")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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RC Release 09.01.00.008
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Adding AVS support for J721S2 SOC.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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RC Release 09.01.00.006
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commit af7c33c103450e06aecf8adba8cbc8c522295be1 upstream.
During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.
Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.
Signed-off-by: Bryan Brattlof <bb@ti.com>
[praneeth@ti.com: cherrypick from v2023.10]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
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AM335x uses a special driver "am335x_spl_bch.c" as SPL
NAND loader. This driver expects 1 sector at a time ECC
and doesn't work well with multi-sector ECC that was implemented
in commit 04fcd2587321.
Switch back to 1 sector at a time read/ECC.
Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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DSP core is going into abnormal state when load callback is called
after starting of DSP core.
Reload of firmware needs core to be stopped first, followed by
load.
So avoid loading of firmware, when core is started.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
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Add PSIL data for AM62P
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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Include the static DMA channel data for ti_sci
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
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The am62px family of SoCs uses the same DDR controller as found on the
am62ax family. Enable this option when building for the am62px family
Signed-off-by: Bryan Brattlof <bb@ti.com>
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