| Age | Commit message (Collapse) | Author |
|---|
|
Use the CONFIG macros to conditionally build the GPIO hogging support in
either the SPL or U-Boot, or both, depending on the configuration. Also
call the GPIO hog probe function in the common SPL board initialization
as an equivalent to adding it to the U-Boot init sequence functions.
Upstream-Status: Backport [1d99e673c752bc7d55aa25b02e050741496f7109]
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
AM62 device has a M4F core in MCU power domain. Support for early boot
is added through remoteoproc driver.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
|
|
make M4F remoteproc a build option.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
|
|
To support u-boot driver model. Retain support legacy way of
doing things if ELM_BASE is defined in <asm/arch/hardware.h>
We could completely get rid of that if all platforms defining
ELM_BASE get rid of that definition. enable CONFIG_SYS_NAND_SELF_INIT
commit 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model
support") upstream
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
|
|
Update the HyperBus calibration sequence to fix the instabilities
seen during calibration.The current calibration sequence is same
as described in J721E TRM[1] which is as follows:
1) Ensure FIFO RAM Auto-init is complete
2) Attempt to read 64 bytes of data from CFI region
for 16 iterations and if data is same in 4 successive iterations
then consider Delay Locked Loop(DLL) is stabilized.
3) Verify DLL lock by verifying MDLL_LOCK and SDL_LOCK bit set in
CFG_DLL_STAT register.
4) Confirm calibration by checking for "QRY" string in CFI region.
Also perform minor cleanup and update am654_hyperbus_calibrate()
to return non-zero value on failure.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
|
|
Flash settings such as Octal-DTR mode and other register configurations
should be resetted before the flash is removed. This would enable
a clean removal and re-plug for later boot stages.
The soft-reset command doesn't restore the flash into 1S mode, so
add support for executing 66h+99h PoR flash reset when in Octal DTR mode.
Datasheet:
https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Releasing the flash into proper state, after the loading completes,
is important for the next stage bootloader/kernel to be able to use
the MTD device. This would enable to reset the device for fresh
use by next boot stage.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Winbond W35N01JW is a SPI NAND flash supporting Octal DTR SPI protocol.
Add op_variants and ctrl_ops_variants for W35N01JW, thus adding all
required Octal DTR ops.
Datasheet:
https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Add implementation of change_protocol() for Winbond's manufacturer_ops,
that executes octal_dtr_enable() and octal_dtr_disable() according
to requested protocol.
Datasheet:
https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Add implementation of octal_dtr_enable() and octal_dtr_disable()
manufacturer_ops for Winbond. To switch to Ocatl DTR mode, setting
programmable dummy cycles and SPI IO mode using the volatile
configuration register is required. To function at max 120MHz SPI clock
in Octal DTR mode, 12 programmable dummy clock cycle setting is
required. (Default number of dummy cycle are 8 clocks)
Set the programmable dummy cycle to 12 clocks, and SPI IO mode to
Octal DTR with Data Strobe in the VCR. Also, perform a READ ID
operation in Octal DTR SPI mode to ensure the switch was successful.
To disable Octal DTR mode, restore the VCR registers to their default
values and verify it using READ ID operation.
Datasheet:
https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Volatile configuration register are a different set of configuration
registers, i.e. they differ from the status registers. A different
SPI instruction is required to write to these registers. Any changes
to the Volatile Configuration Register get transferred directly to
the Internal Configuration Register and instantly reflect on the
device operation.
In Winbond W35N01JW, these volatile configuration register must be
configured in order to switch to Octal DTR SPI mode.
Add support for writing to volatile configuration registers using a
new WRITE_VCR_OP template.
Datasheet:
https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Enable Octal DTR SPI mode, i.e. 8D-8D-8D mode, if the SPI NAND flash
device supports it. Mixed OSPI (1S-1S-8S & 1S-8S-8S), mixed DTR modes
(1S-1D-8D), etc. aren't supported yet.
The method to switch to Octal DTR SPI mode may vary across
manufacturers. For example, for Winbond, it is enabled by writing
values to the volatile configuration register. So, let the
manufacturer's code have their own implementation for switching to
Octal DTR SPI mode.
Check for the SPI NAND device's support for Octal DTR mode using
spinand flags, and if the data_ops and ctrl_ops are 8D-8D-8D, call
change_mode() manufacturer op. If the SPI controller doesn't
supports these modes, the selected data_ops and ctrl_ops will
prevent switching to the Octal DTR mode. And finally update the
spinand protocol and ctrl_ops on success.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
The data_ops_variants and ctrl_ops_variants defined in manufacturer's
code are required again when changing flash modes, because they hold
the op templates for the new protocol. It would be useful to have a
pointer to the device description entry i.e. probed flash's
spinand_info table in the spinand_device struct itself.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Add ctrl_ops_variants, which can be used by the manufacturers' codes
to define their SPI control operation variants. Add a macro to easily
define ctrl_ops_varinats. This can be used to list out all the
supported ctrl ops with their respective protocols by the vendors.
Add spinand_select_ctrl_ops_variant() helper function to search for
a supported ctrl_ops variant with the required SPI protocol in a given
list of variants.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Make use of the ctrl_ops struct, to introduce the usage of templates
in non-page read/write operations as well. These templates are
initialized at the probe time or at SPI modes switches.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Add default ctrl_ops in the core, which can be used when the op
templates are commonly used ones. Till now, the core had used only
fixed ctrl operations, so the default 'ctrl_ops' is just these ops
macros initialized with default arguments. The default protocol is
1S-1S-1S.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Manufacturers have been deviating from the standard SPI operations for
NAND flashes. There have been variations in non-page read/write
instructions too. Additionally, operations, including non-page r/w ops,
vary when flash is in different SPI mode, eg. Octal DTR.
To avoid live-patching in hot-paths or vendor-specific adjustment,
it is better to have a set of operation templates and variants for
non-page read/write operations as well. These would get initialized at
the probe time or when flash changes modes. These would be called
'ctrl_ops'.
To make code better understandable, create two types of op templates
which are: data_ops and ctrl_ops. Reason for having two different type
of templates is the difference in their use cases i.e. it is possible
to have ops of different protocol for read/write/update simulatneously
in the data_ops, but all the ops in the ctrl_ops follow same protocol.
Rename op_templates to data_ops, and the ctrl_ops would be introduced
in later commits.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes
require all instructions to be made in 8D-8D-8D protocol when the
flash is in Octal DTR mode. Hence, storing the current SPI IO mode
becomes necessary for operating the flash and switching between modes.
Store the current SPI IO mode in the spinand struct using a
spinand_protocol enum. This would act as a flag, denoting that the
core should use the given SPI protocol all types of flash operations.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
the cache content to 0xFF (depends on vendor implementation), so we
must fill the page cache entirely even if we only want to program the
data portion of the page, otherwise we might corrupt the BBM or user
data previously programmed in OOB area.
commit mtd: spinand: Handle the case where PROGRAM LOAD does not reset
the cache ("13c15e07eedf26092054c8c71f2f47edb8388310")
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
OSPI controller supports all types of op variants in STIG mode,
only limitation being that the data payload should be less than
8 bytes when not using memory banks.
STIG mode is more stable for operations that send small data
payload and is more efficient than using DMA for few bytes of
memory accesses. It overcomes the limitation of minimum 4 bytes
read from flash into RAM seen in DAC mode.
Use STIG mode for all read and write operations that require
data input/output of less than 8 bytes from the flash, and thereby
support all four phases, cmd/address/dummy/data, through OSPI STIG.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
|
|
buswidth and dtr fields in spi_mem_op are only valid when the
corresponding spi_mem_op phase has a non-zero length. For example,
SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR
phase.
Fix the dtr checks in set_protocol() to ignore empty spi_mem_op
phases, as checking for dtr field in empty phase will result in
false negatives.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
|
|
Check if the parent pll rate is indeed set to target rate, if not
fallback adjusting dividers to get within 5% of requested rate
This is required to set correct rate for DDR PLLs on AM62A resulting in
lower DDR bandwidth when measured with lmbench (bw_mem)
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
|
|
AM62A has a R5F core in MCU voltage domain.
Extend support for R5F remote proc driver on AM62A with compatible
strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
|
|
AM62A SoC has a single C71x DSP subsystem with analytics engine in
main voltage domain. Extend support to AM62A with compatible strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
|
|
In preparation for enabling ethernet for the am62ax at the uboot level,
introduce the initial dma channel settings for the am62ax
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
Introduce the auto-generated clock tree and power domain data needed to
attach the am62a into the power-domain and clock frameworks of uboot
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
Introduce the mach-k3 files needed to properly boot TI's am62a SoC
family of devices
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
Add identification support for TI's am62ax family of SoCs
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
TI's am62a family of SoCs uses a new 32bit DDR controller that shares
much of the same functionality with the existing am64 and j721e
controllers.
Select this controller by default when u-boot is build for the am62a
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
The new 32bit DDR controller for TI's am62a family of SoCs shares much
of the same functionality with the existing 16bit (am64) and 32bit
(j721e) controllers, so this patch reorganizes the existing
auto-generated macros for the 16bit and 32bit controllers to make room
for the macros for the am62a's controller
This patch consists mostly of header/macro renames and additions with a
new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new
macros during compilation.
Signed-off-by: Bryan Brattlof <bb@ti.com>
|
|
Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.
For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI Driver
when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices. This operates by
default in a 32 bit mode causing it to always align all data to 4 bytes
from a 4byte aligned address. In some flash chips like cypress for example
if we try to read some regs in DAC mode then it keeps sending the value of
the first register that was requested and inorder to read the next reg, we
have to stop and re-initiate a new transaction.
This causes wrong registers values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less then
prefer STIG mode for such small reads.
[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
|
|
Setup the Addr bit field while issuing register reads in STIG mode. This
is needed for example flashes like cypress define in their transaction
table that to read any register there is 1 cmd byte and a few more address
bytes trailing the cmd byte. Absence of addr bytes will obviously fail
to read correct data from flash register that maybe requested by flash
driver because the controller doesn't even specify which address of the
flash register the read is being requested from.
Also update some LSB macros to use BIT(n) macro instead for better
readability.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
This is a partial backport of commit
1e2b8139d95ea924d645886b323be7748579a6d1 upstream:
"move CQSPI_STIG_DATA_LEN_MAX macro to cqspi header file."
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
Commit 1c3dd193b5ba76da9d5b2b422d04605321a91c94 upstream.
The nor->ready() and spansion_sr_ready() introduced earlier in this
series are used for multi-die package parts.
The nor->quad_enable() sets the volatile QE bit on each die.
The nor->erase() is hooked if the device is not configured to uniform
sectors, assuming it has 32 x 4KB sectors overlaid on bottom address.
Other configurations, top and split, are not supported at this point.
Will submit additional patches to support it as needed.
The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
Commit 72151ad10f8dcc3c86084259b227a7d70cc79473 upstream.
Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.
Cypress chips support B8h to disable 4-byte addressing mode instead of
SPINOR_OP_EX4B(E9h).
This patch defines new opcode and updates set_4byte() to support
enable/disable 4-byte addressing mode for Cypress chips.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
Commit d2d79895da1b80275fe0ffd84d697519c73c924d upstream.
The spansion_sr_ready() reads status register 1 by Read Any Register
commnad. This function is called from Flash specific hook with die address
and dummy cycles to support multi-die package parts from Spansion/Cypress.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
Commit 24b1e2c690fb953a3a981a282e37de5a0f1a98b1 upstream.
For dual/quad die package devices from Spansion/Cypress, the device's
status needs to be checked by reading status registers in all dies, by
using Read Any Register command. To support this, a Flash specific hook
that can overwrite the legacy status check is needed.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
Commit a4aa9b7522dc67745795c1e2a76115a616da00ea upstream.
Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in
CFR1 volatile.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
Commit 2d20f344858265722452d06fe7a5f86ca736b86d upstream.
Some of Spansion/Cypress chips support Read/Write Any Register commands.
These commands are mainly used to write volatile registers and access to
the registers in second and subsequent die for multi-die package parts.
The Read Any Register instruction (65h) is followed by register address
and dummy cycles, then the selected register byte is returned.
The Write Any Register instruction (71h) is followed by register address
and register byte to write.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
Commit c95a914aed7d8025b3877b04272aecf4e1b56ea4 upstream.
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single
die)
https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (registration
required).
https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522
https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503
S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable
sector architecture. By default, the 512Mb and 1Gb, single-die package
parts are configured to non-uniform that 4KB sectors overlaid on bottom
address. To support this, an erase hook makes overlaid sectors appear as
uniform sectors. The 2Gb, dual-die package parts are configured to
uniform
by default.
Tested on Xilinx Zynq-7000 FPGA board.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
|
After performing DFS on A72, the clk-k3 driver causes the reboot to fail
due to fault clock re-initialization
The clk-k3.c driver performs PLL setup based on the difference between
the requested clock rate and current clock rate. If the difference is
found to be more that 50%, in that case it recurses to the clock's parent
for changing its frequency and setting up the PLL. If the difference is
found to be less than that, it assumes that it is a rounding error in the
divider and tries to accommodate for that without touching the parent
clocks.
So, 5% to 50% difference, it assumes it to be a rounding error. From 50%
difference onward it treats it as a HSDIV+PLL configuration case and
sets everything correctly.
So when a fresh boot happens, the A72 clock frequency is found to be at
19.2MHz, which is way less than 2GHz and hence it crosses 50% barrier and
gets properly setup. But when we change the A72 frequency to 1.5 GHz
through DFS, the difference is only of 25% (<50%). So, when we do a
reboot, it doesn't configure the parent clocks and PLLs, it just tries to
make the value close to 2GHz, but that doesn't work.
So, reduce the threshold from 50% to 12.5%, to reconfigure the clocks
correctly at reboot, allowing to boot up after a DFS operation.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
|
|
U-Boot is fail to boot class U1 UHS SD cards (such as microcenter)
due to incorrect OTAP and ITAP delay select values. Update OTAP and
ITAP delay select values based on recommeded RIOT values to fix boot
issue.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
|
|
Current entries in the ti_sci_static_data for J784S4 is incorrect
due to update in rm-cfg and this caused DMA failures in SPL while
trying OSPI boot with DMA for J784S4, fix the incorrect entries.
Fixes: 0b6d1af19aae ("drivers: dma: Add support for J784S4")
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
|
|
When devm_ti_sci_get_of_resource() call fails to return a valid
pointer for ringacc->rm_gp_range, the error was being ignored
and returned success.Fix the return and also add an error print
for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
|
|
For the TI SoCs affected by errata i2329, enable MDIO manual
mode by default
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
For the TI SoCs affected by errata i2329, enable MDIO manual
mode by default
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
In certain TI SoCs, on the CPSW and ICSS peripherals, there is
a possibility that the MDIO interface returns corrupt data on
MDIO reads or writes incorrect data on MDIO writes. There is also
a possibility for the MDIO interface to become unavailable until
the next peripheral reset.
The workaround is to configure the MDIO in manual mode and disable the
MDIO state machine and emulate the MDIO protocol by reading and writing
appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller
to manipulate the MDIO clock and data pins.
More details about the errata i2329 and the workaround is available in:
https://www.ti.com/lit/er/sprz487a/sprz487a.pdf
Add implementation to disable MDIO state machine, configure MDIO in manual
mode and provide software MDIO read and writes via MDIO bitbanging. Allow
the MDIO to be initialized based on the need for manual mode.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
|
|
ESM MCU masks must be set to 0h so that PMIC can handle errors
that require attention for example SYS_SAFETY_ERRn. The required bits
must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK.
If PMIC expected to handle errors, make sure EVM is configured to
connect SOC_SAFETY_ERRz (Main) to the PMIC.
Note that even though the User Guide for TPS65941 for J721E mentions
that these bits are reset to 0h; it is not reflected once board boots to
kernel, possibly due to NVM configurations. Eithercase, it is best to
account for this from R5 SPL side as well.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Add support for j784s4-wiz-10g device which has two core reference
clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional
mux selection option.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
|
|
Move device specific data into OF data structure so it
is easier to maintain and we can get rid of if statements.
Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u
Cc: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
|
